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Embed Python for use with HDL. Wanted to show how easy it is to use Python together with Verilog or VHDL. With just a few lines the Python interpreter can be embedded and call tasks or functions in SystemVerilog. I am using the proprietary simulator Questasim in this example. The SystemVerilog code looks like this. The C code looks like this. Include #include vpi user.h #include pythonEmbedded.h static PyObject * c write(PyObject *self, PyObject *args) { int address,data; if(! Easiest way to try it out:.

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Embed Python for use with HDL. Wanted to show how easy it is to use Python together with Verilog or VHDL. With just a few lines the Python interpreter can be embedded and call tasks or functions in SystemVerilog. I am using the proprietary simulator Questasim in this example. The SystemVerilog code looks like this. The C code looks like this. Include #include vpi user.h #include pythonEmbedded.h static PyObject * c write(PyObject *self, PyObject *args) { int address,data; if(! Easiest way to try it out:.

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andreaslindh | andreaslindh.wordpress.com Reviews

https://andreaslindh.wordpress.com

Embed Python for use with HDL. Wanted to show how easy it is to use Python together with Verilog or VHDL. With just a few lines the Python interpreter can be embedded and call tasks or functions in SystemVerilog. I am using the proprietary simulator Questasim in this example. The SystemVerilog code looks like this. The C code looks like this. Include #include vpi user.h #include pythonEmbedded.h static PyObject * c write(PyObject *self, PyObject *args) { int address,data; if(! Easiest way to try it out:.

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andreaslindh.wordpress.com

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Since I move ar… | andreaslindh

https://andreaslindh.wordpress.com/2011/12/18/since-i-move-ar

Since I move ar…. Since I move around a bit, I have tcsh script that configure my emacs to the bare minimum of what I need as an ASIC Designer. That is a decently new versions of VHDL, SPECMAN, and Verilog mode. To check is out, have a look at. Http:/ github.com/oddball/cfgEmacs/blob/master/cfgEmacs.sh. Trackback ( 0 ). Comments ( 0 ). Leave a Reply Cancel reply. Enter your comment here. Fill in your details below or click an icon to log in:. Address never made public). Notify me of new comments via email.

2

Synthesizable Generic Memory | andreaslindh

https://andreaslindh.wordpress.com/2011/09/12/synthesizable-generic-memory

A Verilog module that can be specialised from a simulation model to a vendor memory, without manually changing a line of RTL! There are also significant SCM and reuse, advantages to using a generic memory. The general principle is simple. Instantiate a module that depending on parameters (generics) instantiates different memory models. If you have no vendor models, instantiate a generic memory model. If you have vendor models, have a simple switch statement that instantiates the memory of the correct size.

3

Questasim/Modelsim VHDL warnings | andreaslindh

https://andreaslindh.wordpress.com/2011/12/08/questasimmodelsim-vhdl-warnings-2

When using Questasim/Modelsim there is a easy trick to get rid of the initial warnings like. Warning: NUMERIC STD.TO INTEGER: metavalue detected, returning 0. Time:0 fs. Warning: There is an ‘U’ ’X’ ’W’ ’Z’ ’-‘ in an arithmetic operand, the result will be ‘X'(es). Time:0 fs. Warning: CONV INTEGER: There is an ‘U’ ’X’ ’W’ ’Z’ ’-‘ in an arithmetic operand. Time:0 fs. Make a file called shutup.do. Call the file with do shutup.do. Trackback ( 0 ). Comments ( 1 ). February 3rd, 2012. Leave a Reply Cancel reply.

4

October | 2011 | andreaslindh

https://andreaslindh.wordpress.com/2011/10

Archive for October, 2011. Auto Dependency Makefile Example. There are a lot of “Hello World” examples out there, but I seldom find them complete. There for I made one, mostly for myself. It automatically updates the dependencies from all source files. So in my example I have a src directory that looks like this:. Ls -1 src/ classA.cc classA.hh classB.cc classB.hh main.cc. The Makefile looks like this. To see how it works, the easiest thing is to do:. Http:/ mad-scientist.net/make/autodep.html. Follow &l...

5

IP-XACT for Emacs | andreaslindh

https://andreaslindh.wordpress.com/2011/12/19/ip-xact-for-emacs

As we all know, real ASIC Designers use Emacs. Occasionally however good thing come around that does not support Emacs directly. One of these things are the Spirit Consortium IP-XACT http:/ www.accellera.org/activities/committees/ip-xact. Granted I never really liked anything in IP-XACT, but the possiblitly to use it to describe Registers. But an Industry standard for that, is badly needed. Validating xml files for IP-XACT is done with XSD files. So validating a yourRegisterFile.xml can be done with.

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Embed Python for use with HDL. Wanted to show how easy it is to use Python together with Verilog or VHDL. With just a few lines the Python interpreter can be embedded and call tasks or functions in SystemVerilog. I am using the proprietary simulator Questasim in this example. The SystemVerilog code looks like this. The C code looks like this. Include #include vpi user.h #include pythonEmbedded.h static PyObject * c write(PyObject *self, PyObject *args) { int address,data; if(! Easiest way to try it out:.

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