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Adventures in ASIC Digital Design | Tricks and Tips for ASIC Digital Designers | asicdigitaldesign.wordpress.com Reviews
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Tricks and Tips for ASIC Digital Designers
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The Double Edge Flip Flop | Adventures in ASIC Digital Design
https://asicdigitaldesign.wordpress.com/2007/07/31/the-double-edge-flip-flop
Adventures in ASIC Digital Design. Tricks and Tips for ASIC Digital Designers. Arithmetic Tips and Tricks #1. The Double Edge Flip Flop. July 31, 2007. Sometimes it is necessary to use both the rising and the falling edge of the clock to sample the data. This is sometimes needed in many DDR applications (naturally). The double edge flop is sometimes depicted like that:. What’s wrong with the above approach? Here is a cool circuit that can help solve this problem:. Posted in Cool Circuits. Until now I hav...
Dual Edge Binary Counters + Puzzle | Adventures in ASIC Digital Design
https://asicdigitaldesign.wordpress.com/2009/06/24/dual-edge-binary-counters
Adventures in ASIC Digital Design. Tricks and Tips for ASIC Digital Designers. Laquo; Reordering Nets for Low Power. Real World Examples #5 – Clock Divider by 5. Dual Edge Binary Counters Puzzle. June 24, 2009. I lately came across the need to use a dual edge counter, by this I mean a counter which is counting both on the rising and on the falling edge of the clock. The limitation is that one has to use only normal single edge sensitive flops, the kind you find in each library. Posted in Cool Circuits.
Parametrized Reset Values | Adventures in ASIC Digital Design
https://asicdigitaldesign.wordpress.com/2009/04/19/parametrized-reset-values
Adventures in ASIC Digital Design. Tricks and Tips for ASIC Digital Designers. Laquo; Puzzle #14 – Multipliers. Reordering Nets for Low Power. April 19, 2009. For some odd reason some designers refuse to use parametrized blocks. I have no idea what are the reasons for such an opinion, but here is a good example why one would want to decide for the usage of parameters. The better option is to send the reset value as a parameter, which if it wasn’t clear by now, is the way to go. April 20, 2009 at 4:29 am.
June | 2009 | Adventures in ASIC Digital Design
https://asicdigitaldesign.wordpress.com/2009/06
Adventures in ASIC Digital Design. Tricks and Tips for ASIC Digital Designers. Archive for June, 2009. Dual Edge Binary Counters Puzzle. June 24, 2009. I lately came across the need to use a dual edge counter, by this I mean a counter which is counting both on the rising and on the falling edge of the clock. The limitation is that one has to use only normal single edge sensitive flops, the kind you find in each library. The figure below depicts the counter:. The value in each of the n-bit arrays does not.
Real World Examples #5 – Clock Divider by 5 | Adventures in ASIC Digital Design
https://asicdigitaldesign.wordpress.com/2009/08/26/real-world-examples-5-clock-divider-by-5
Adventures in ASIC Digital Design. Tricks and Tips for ASIC Digital Designers. Laquo; Dual Edge Binary Counters Puzzle. Real World Examples #5 – Clock Divider by 5. August 26, 2009. Here is a neat little circuit that was used in an actual project a long, long time ago (in a galaxy far, far away…). Basically, the circuit is made out of a 3-bit counter, that counts from 000 to 100 and then resets. Signal ‘X’. Goes high when the value of the counter is either 000, 001 or 010. Signal ‘Y’. Is a sample on the.
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VLSI - ASIC Digital Design FAQs: 6/7/09 - 6/14/09
http://vlsifaqs.blogspot.com/2009_06_07_archive.html
VLSI - ASIC Digital Design FAQs. Next Post: "Let us know your interests". You can mail your Queries and Suggestions at vlsihelio@gmail.com. June 7, 2009. How to install Multi operating systems (Solaris, RHEL, CENTOS, FEDORA, SUSE) on single or multiple hard disks? Don't forget that Fedora always need / (root) label to get installed, so change the other OS's. Labels to something else as /1 or /12 or /123, etc. by using any partition software like paragon partition software or something else. If you constr...
VLSI - ASIC Digital Design FAQs: 3/30/08 - 4/6/08
http://vlsifaqs.blogspot.com/2008_03_30_archive.html
VLSI - ASIC Digital Design FAQs. Next Post: "Let us know your interests". You can mail your Queries and Suggestions at vlsihelio@gmail.com. April 4, 2008. Physical Design For Novices. Welcome to the Physical Design. First of all what are the basics you need to know:. Digital Design (Basic and Advanced). Integrated Electronics - Millman and Halkias. Digital Design - Morris Mano. Digital Logic and Computer Design - Morris Mano. Principles of CMOS Vlsi Design - Neil Weste. Microelectronic Circuits - Sedra/S...
VLSI - ASIC Digital Design FAQs: 8/3/08 - 8/10/08
http://vlsifaqs.blogspot.com/2008_08_03_archive.html
VLSI - ASIC Digital Design FAQs. Next Post: "Let us know your interests". You can mail your Queries and Suggestions at vlsihelio@gmail.com. August 9, 2008. In most of the design, generally memory block has very less time margin to meet setup or hold requirements, then how you'll be able to meet timings? By putting a latch before the memory or you can say by applying "time borrowing" concept. What is the netlistless floorplan? And what is the use of it? Subscribe to: Posts (Atom). Nov 1 - Nov 8.
The Tao Of ASICs: December 2007
http://asictao.blogspot.com/2007_12_01_archive.html
The Tao Of ASICs. An ASIC, SoC and EDA Blog. Monday, December 31, 2007. Combining ASIC, FPGA and Structured ASIC On A Single SoC. The availability of structured ASIC IP for use within standard SoC creates yet another option for ASIC design houses seeking to balance NRE, per-unit cost and time-to-market. You can see the announcement by ChipX here. Think of the advantages that each approach bring to the table:. FPGA : Highly configurable, Fast Time-to-Market , Low performance. Just flip the equation. Funct...
The Tao Of ASICs: June 2009
http://asictao.blogspot.com/2009_06_01_archive.html
The Tao Of ASICs. An ASIC, SoC and EDA Blog. Wednesday, June 03, 2009. EDA Standardization: The Next Wave Is Here! In one of my earlier posts ( EDA Standards I'd Love To See. I argued for a standard for interconnect extraction rule from that will be used by the extraction tool. I quote:. This standard is the first of many to come (I' m expecting that DRC and LVS rule formats are next in line). Posted by Aditya Ramachandran. Links to this post. Subscribe to: Posts (Atom). View my complete profile. Harry &...
The Tao Of ASICs: July 2008
http://asictao.blogspot.com/2008_07_01_archive.html
The Tao Of ASICs. An ASIC, SoC and EDA Blog. Friday, July 04, 2008. Design For Flexibility : Deep Data and Function Access Is A Must For EDA Tools. Advancing the State Of The Art :. Maintain the Status Quo :. Posted by Aditya Ramachandran. Links to this post. Subscribe to: Posts (Atom). Aditya Ramachandran is interested in technology in all its forms and the disruptive business models that it enables. View my complete profile. Get The Tao (Email). Design For Flexibility : Deep Data and Function Ac.
VLSI - ASIC Digital Design FAQs: How to install Multi operating systems (Solaris, RHEL, CENTOS, FEDORA, SUSE) on single or multiple hard disks? -- Part2
http://vlsifaqs.blogspot.com/2009/05/how-to-install-multi-operating-systems_24.html
VLSI - ASIC Digital Design FAQs. Next Post: "Let us know your interests". You can mail your Queries and Suggestions at vlsihelio@gmail.com. May 24, 2009. How to install Multi operating systems (Solaris, RHEL, CENTOS, FEDORA, SUSE) on single or multiple hard disks? So till so far we are done with Solaris and RHEL. If in case, you had not mentioned during RHEL installation about Solaris, even though you need not to worry. Let the system get booted in RHEL and edit this file /boot/grub/menu.lst. Check the l...
VLSI - ASIC Digital Design FAQs: 5/25/08 - 6/1/08
http://vlsifaqs.blogspot.com/2008_05_25_archive.html
VLSI - ASIC Digital Design FAQs. Next Post: "Let us know your interests". You can mail your Queries and Suggestions at vlsihelio@gmail.com. May 27, 2008. Regarding SKEW and CLK Timeperiod. On Thu, May 22, 2008 at 9:32 PM, helio vlsi vlsihelio@gmail.com. Yes, its possible. Your skew can be greater than clock period. But i think you'll never able to see it in your design, until unless you make the design purposefully to give that much of skew or when someone do the CTS, who doesn't know it at all. Things t...
VLSI - ASIC Digital Design FAQs: 4/13/08 - 4/20/08
http://vlsifaqs.blogspot.com/2008_04_13_archive.html
VLSI - ASIC Digital Design FAQs. Next Post: "Let us know your interests". You can mail your Queries and Suggestions at vlsihelio@gmail.com. April 18, 2008. INTRODUCTION TO ASIC - Part-2. Field Programmable Gate Arrays:. None of the layers is customized. Basic logic cells and interconnect can be programmed. Basic cells can be SRAM based, Flash Memory based or fuse-based (One time programmable). Advantages and Disadvantages of FPGA:. A shorter time to market. Ability to re-program in the field to fix bugs.
VLSI - ASIC Digital Design FAQs: 9/14/08 - 9/21/08
http://vlsifaqs.blogspot.com/2008_09_14_archive.html
VLSI - ASIC Digital Design FAQs. Next Post: "Let us know your interests". You can mail your Queries and Suggestions at vlsihelio@gmail.com. September 20, 2008. What is the netlistless floorplan? And what is the use of it? Netlistless floorplan is a dummy floorplan with all available information and guesses by the previous experiences, to have a look into the possible coming difficulties in making the chip a way to Fab. Subscribe to: Posts (Atom). Things to REALISE - Balance in Life. Nov 1 - Nov 8. May 25...
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ASIC Design News
FD-SOI the Synapse Way. Monday May 18, 2015. Last week I talked to Marco Brambilla of Synapse Design. Synapse is a design services company headquartered in Silicon Valley. It was founded in 2003 by Satish Bagalkotkar and has been profitable since the beginning. Today it has over 700 people. — Read More. S2C Single VU440 Prodigy FPGA Prototyping Board for Xilinx Virtex UltraScale 440 FPGA Now Available. Monday May 18, 2015. Vendor independent HDL code for image processing using FPGA/ ASICs. The Six Sigma ...
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Adventures in ASIC Digital Design | Tricks and Tips for ASIC Digital Designers
Adventures in ASIC Digital Design. Tricks and Tips for ASIC Digital Designers. Real World Examples #5 – Clock Divider by 5. August 26, 2009. Here is a neat little circuit that was used in an actual project a long, long time ago (in a galaxy far, far away…). Basically, the circuit is made out of a 3-bit counter, that counts from 000 to 100 and then resets. Signal ‘X’. Goes high when the value of the counter is either 000, 001 or 010. Signal ‘Y’. Is a sample on the. Edge of ‘Y’. How would you fix it in RTL?
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ASIC DESIGN and MARKETING provides an objective source of information and guidance. We have worked closely with multiple FPGA and EDA manufacturers creating new products for timing driven Synthesis/Compilation, Simulation, and Automated PlaceRoute. Dr Soderman has also provided expert testimony in Federal Courts protecting intellectual property in patent and ASIC business litigation cases. Located in the heart of Silicon Valley, California.
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