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SVA Sequences IV – Multiple Clock Domains/ Multi-clocked Sequence | VLSI Pro

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SVA Sequences IV – Multiple Clock Domains/ Multi-clocked Sequence. Posted on November 1, 2013. In Assertion Based Verification. Multi-clocked sequences are built by concatenating multiple single clocked sequences in different clock domains using following operators. Single delay concatenation operator (# 1). Zero-delay concatenation operator (# 0). Single delay concatenation operator (# 1). Sequence mult seq1; @(posedge clk1) seq1 # 1 @(posedge clk2) seq2; endsequence: mult seq1. 1 @(posedge clk2) seq2;.

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Assertion Based Verification | VLSI Pro

http://vlsi.pro/category/front-end/verification/assertion-based-verification

February 4, 2015. Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, [.]. SVA Properties IV : Until Property. March 12, 2014. A property is called “until property” if it uses one of the below until operators. until s until until with s until with Until properties are categorized as Overlapped & [.]. SVA Properties III : Implication. March 11, 2014. November 22, 2013.

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SVA Properties II : Types | VLSI Pro

http://vlsi.pro/sva-properties-ii-types

SVA Properties II : Types. Posted on November 22, 2013. In Assertion Based Verification. Properties which contain sequence definitions are called sequence properties.Sequence properties are of three types. If there is no finite prefix that witnesses inability to match the sequence expr,. Evaluates to true. The following example shows a weak sequential property p1. Property p1; weak(b # 1 c); endproperty weak assert : assert property (@(posedge clk) a - p1);. An evaluation attempt of. This means, property...

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Front End | VLSI Pro

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SV Constraint random value generation : Introduction. May 1, 2015. System Verilog supports three different approaches in verification as follows. 1. Directed Testing 2. Random Testing 3. Directed Random/Constrained Random Testing Directed testing is the traditional [.]. System Verilog : Mailbox. February 23, 2015. February 4, 2015. System Verilog : Array Reduction & Array Ordering Methods. July 5, 2014. System Verilog : Array querying system functions. July 1, 2014. System Verilog : Queues. June 26, 2014.

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SVA Properties III : Implication | VLSI Pro

http://vlsi.pro/sva-properties-implication

SVA Properties III : Implication. Posted on March 11, 2014. In Assertion Based Verification. Property expr : = . sequence expr - property expr sequence expr = property expr. There are two types of implication called overlapped and non-overlapped. Property nand prop; nand sig o -! Nand a i & nand b i); endproperty; assert nand: assert property(nand prop);. In the overlapped ( - ) implication, from a given start point antecedent will be evaluated. If there is:. Latest posts by Sini Balakrishnan ( see all.

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General | VLSI Pro

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May 1, 2015. SV Constraint random value generation : Introduction. May 1, 2015. System Verilog supports three different approaches in verification as follows. 1. Directed Testing 2. Random Testing 3. Directed Random/Constrained Random Testing Directed testing is the traditional [.]. February 4, 2015. Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, [.]. System Veri...

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Scripts | VLSI Pro

http://vlsi.pro/category/back-end/scripts

Creating .lib file from verilog. December 13, 2012. Creating a dummy .lib file is something every physical design engineer has done now and then. If you have a verilog model of the block available, your task gets easier. The following script automates [.]. SV Constraint random value generation : Introduction. System Verilog : Mailbox. Minimum Pulse Width Check. On Physical Design Flow III:Clock Tree Synthesis. On Code Coverage Fundamentals. On Physical Design Flow III:Clock Tree Synthesis.

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Equivalence Checking | VLSI Pro

http://vlsi.pro/category/front-end/verification/equivalence-checking

Equivalency Checking Flow – Basics. June 11, 2014. Once RTL is released, the next step is to go for synthesis to get a gate-level representation of the design. This is called synthesized netlist. Assumption is that synthesized netlist has the same [.]. Sequential Equivalence Checking for high performance design. November 6, 2012. SV Constraint random value generation : Introduction. System Verilog : Mailbox. Minimum Pulse Width Check. On Physical Design Flow III:Clock Tree Synthesis. VLSI Pro provides in...

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SVA Sequences I : Basics | VLSI Pro

http://vlsi.pro/sva-sequences-basic-concepts

SVA Sequences I : Basics. Posted on October 10, 2013. In Assertion Based Verification. Sequence is a finite list of System Verilog Boolean expressions which matches along a finite interval of consecutive clock ticks. It evaluates Boolean expressions to true in each clock tick till the last expression. The major difference of sequence from a property is that, sequence does not have a success/fail status. Instead, it simply matches or not. Following is a very simple sequence. Inc or dec expression. Sequenc...

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SVA Properties I : Basics | VLSI Pro

http://vlsi.pro/sva-properties-basics

SVA Properties I : Basics. Posted on November 21, 2013. In Assertion Based Verification. Property construct syntax (LRM). Property lvar port direction. Property lvar port direction. Cycle delay const range. Cycle delay const range. List of variable decl. Ps or hierarchical property. Property list of arguments. A property can be referenced/instantiated in verification directive statements like assert, assume, cover, or restrict statement or in a property as shown below. Instantiated my prop1 and my prop2.