AZAKS.EEW.TECHNION.AC.IL
About | Ayal ZaksResearch Interests Compiler optimizations Parallel architectures, including thread-level, data-level and instruction-level parallelism Compiler ...
http://azaks.eew.technion.ac.il/
Research Interests Compiler optimizations Parallel architectures, including thread-level, data-level and instruction-level parallelism Compiler ...
http://azaks.eew.technion.ac.il/
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About | Ayal Zaks | azaks.eew.technion.ac.il Reviews
https://azaks.eew.technion.ac.il
Research Interests Compiler optimizations Parallel architectures, including thread-level, data-level and instruction-level parallelism Compiler ...
Committees | CC2016
http://cc2016.eew.technion.ac.il/committees
International Conference on Compiler Construction. CC2016 Call for papers. Intel and Technion, Israel. IMDEA SW Institute and T.U. Madrid-UPM, Spain. Raj Barik, Intel Labs, Santa Clara, CA. Uday Bondhugula, IIS Bangalore. Matthew Flatt, University of Utah. Maria Garzaran, UIUC and Intel. Laurie Hendren, McGill U. Manuel Hermenegildo, IMDEA and T.U. Madrid. Xavier Leroy, INRIA. Ondrej Lhotak, U. of Waterloo. Francesco Logozzo, Facebook. Antoine Miné, Ecole Normale Supérieure, Paris. Jose Morales, IMDEA SW.
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About | Ayal Zaks
Parallel architectures, including thread-level, data-level and instruction-level parallelism. Compiler middle-end and back-end analysis and transformations targeting architectures to exploit such parallelism. Joined Intel Israel (Haifa) on Dec. 2011, working on LLVM-based compiler optimizations for Intel platforms. Co-supervising PhD and MSc students; referee of theses. Organizing conferences, including CATC. Spent a short sabbatical at Princeton University during the summer of 2011.
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