blog.bejoythomas.com

Bejoy Thomas

Friday, August 28, 2015. Sunday, July 26, 2015. Saturday, April 18, 2015. Delhi and NCR Region. Tuesday, December 29, 2009. Master ***** JK Flip Flop. Use ieee.std logic 1164.all;. Entity master ***** jk is. Port(j,k,clk:in std logic;q1,q1x,z1x:inout std logic;. Q2,q2x,z2x: inout std logic);. End master ***** jk;. Architecture arc of master ***** jk is. Z1x =(j and (not q2) or ( not k)and q2);. Q1 =z1x after 5 ns;. Q1x =not z1x after 5ns;. Z2x =(q1 and (not q2) or ( not q1x)and q2);. Q2 =z2x after 5 ns;.

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Friday, August 28, 2015. Sunday, July 26, 2015. Saturday, April 18, 2015. Delhi and NCR Region. Tuesday, December 29, 2009. Master ***** JK Flip Flop. Use ieee.std logic 1164.all;. Entity master ***** jk is. Port(j,k,clk:in std logic;q1,q1x,z1x:inout std logic;. Q2,q2x,z2x: inout std logic);. End master ***** jk;. Architecture arc of master ***** jk is. Z1x =(j and (not q2) or ( not k)and q2);. Q1 =z1x after 5 ns;. Q1x =not z1x after 5ns;. Z2x =(q1 and (not q2) or ( not q1x)and q2);. Q2 =z2x after 5 ns;.

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Bejoy Thomas | blog.bejoythomas.com Reviews

https://blog.bejoythomas.com

Friday, August 28, 2015. Sunday, July 26, 2015. Saturday, April 18, 2015. Delhi and NCR Region. Tuesday, December 29, 2009. Master ***** JK Flip Flop. Use ieee.std logic 1164.all;. Entity master ***** jk is. Port(j,k,clk:in std logic;q1,q1x,z1x:inout std logic;. Q2,q2x,z2x: inout std logic);. End master ***** jk;. Architecture arc of master ***** jk is. Z1x =(j and (not q2) or ( not k)and q2);. Q1 =z1x after 5 ns;. Q1x =not z1x after 5ns;. Z2x =(q1 and (not q2) or ( not q1x)and q2);. Q2 =z2x after 5 ns;.

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blog.bejoythomas.com

1

Bejoy Thomas: Master Slave JK Flip Flop

http://blog.bejoythomas.com/2009/12/master-slave-jk-flip-flop.html

Tuesday, December 29, 2009. Master Slave JK Flip Flop. Use ieee.std logic 1164.all;. Entity master slave jk is. Port(j,k,clk:in std logic;q1,q1x,z1x:inout std logic;. Q2,q2x,z2x: inout std logic);. End master slave jk;. Architecture arc of master slave jk is. Z1x =(j and (not q2) or ( not k)and q2);. Q1 =z1x after 5 ns;. Q1x =not z1x after 5ns;. Z2x =(q1 and (not q2) or ( not q1x)and q2);. Q2 =z2x after 5 ns;. Q2x =not z2x after 5ns;. February 28, 2011 at 10:12 PM. Can u dig it. March 6, 2012 at 1:21 AM.

2

Bejoy Thomas: Delhi & NCR Region

http://blog.bejoythomas.com/2015/04/delhi-ncr-region.html

Saturday, April 18, 2015. Delhi and NCR Region. Subscribe to: Post Comments (Atom). I'm a 22 year old Electronics and Communication Engineer. This is my personal weblog and is a collection of my interests, ideas, thoughts, opinions, my latest project news and anything that I feel like sharing with you. View my complete profile. Simple template. Powered by Blogger.

3

Bejoy Thomas: VHDL code for JK Flip Flop

http://blog.bejoythomas.com/2009/12/vhdl-code-for-jk-flip-flop.html

Wednesday, December 23, 2009. VHDL code for JK Flip Flop. Use ieee.std logic 1164.all;. Entity bejoy jkff is. Port(j,k,clk:in std logic;q,q1,z:inout std logic);. End bejoy jkff;. Architecture arc of bejoy jkff is. December 31, 2011 at 10:30 PM. Nice one.thanks for sharing. January 2, 2012 at 9:31 PM. March 11, 2012 at 4:08 AM. Thanks for posting this. October 10, 2012 at 8:07 PM. Thank you for posting dude! December 2, 2012 at 2:30 AM. When J=1 and K=1, how will the values toggle? View my complete profile.

4

Bejoy Thomas: VHDL code for Even Parity Generator

http://blog.bejoythomas.com/2009/12/vhdl-code-for-even-parity-generator.html

Wednesday, December 23, 2009. VHDL code for Even Parity Generator. Use ieee.std logic 1164.all;. Entity bejoy ep is. Port(x,y,z:in std logic;. P:out std logic);. End bejoy ep;. Architecture a of bejoy ep is. April 27, 2012 at 2:25 AM. Humari toh humare teacher ne waat lga di thi. Subscribe to: Post Comments (Atom). View my complete profile. Simple template. Powered by Blogger.

5

Bejoy Thomas: VHDL code for SR Flip Flop

http://blog.bejoythomas.com/2009/12/vhdl-code-for-sr-flip-flop.html

Wednesday, December 23, 2009. VHDL code for SR Flip Flop. Use ieee.std logic 1164.all;. Entity bejoy rsff is. Port(s,r,clk:in std logic;q,q1,z:inout std logic);. End bejoy rsff;. Architecture arc of bejoy rsff is. April 4, 2011 at 10:09 AM. Helped me a lot in lab! February 15, 2013 at 9:05 PM. Very nice but you should have written it in terms of edge trigger and not the level trigger.For detecting EDGE the construst is rising edge(clk). February 19, 2013 at 9:48 PM. Thank you so much!

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Friday, August 28, 2015. Sunday, July 26, 2015. Saturday, April 18, 2015. Delhi and NCR Region. Tuesday, December 29, 2009. Master Slave JK Flip Flop. Use ieee.std logic 1164.all;. Entity master slave jk is. Port(j,k,clk:in std logic;q1,q1x,z1x:inout std logic;. Q2,q2x,z2x: inout std logic);. End master slave jk;. Architecture arc of master slave jk is. Z1x =(j and (not q2) or ( not k)and q2);. Q1 =z1x after 5 ns;. Q1x =not z1x after 5ns;. Z2x =(q1 and (not q2) or ( not q1x)and q2);. Q2 =z2x after 5 ns;.

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