opensocfabric.org
OpenSoC Fabric - Diagram
http://www.opensocfabric.org/diagram.php
Lawrence Berkeley National Lab. Co-Design for Exascale (CoDEx). Computer Architecture Lab (CAL). SoC for HPC Workshop. The OpenSoC Fabric is an ongoing project to create a open source network-on-chip generator capable of creating a synthesizeable network for connecting processors, memory and I/O devices. Completely Hierarchical and Parameterizable. It'll blow your mind. Being written and designed in Chisel, OpenSoC Fabric.
opensocfabric.org
OpenSoC Fabric - Abstract
http://www.opensocfabric.org/abstract.php
Lawrence Berkeley National Lab. Co-Design for Exascale (CoDEx). Computer Architecture Lab (CAL). SoC for HPC Workshop. The OpenSoC Fabric is an ongoing project to create a open source network-on-chip generator capable of creating a synthesizeable network for connecting processors, memory and I/O devices. Infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, and follows object-oriented design and functional programming to make...
opensocfabric.org
OpenSoC Fabric - About the Team
http://www.opensocfabric.org/about.php
Lawrence Berkeley National Lab. Co-Design for Exascale (CoDEx). Computer Architecture Lab (CAL). SoC for HPC Workshop. The OpenSoC Fabric is an ongoing project to create a open source network-on-chip generator capable of creating a synthesizeable network for connecting processors, memory and I/O devices. George is a postdoctoral research fellow at LBNL and is a member of the CAL group. His past work focuses on on-chip network with numerous contributions to flow control, congestion, allocation, and co...
sifive.com
SiFive - Jobs
https://www.sifive.com/about/jobs
RISC-V Chips Are Here — Get Your Own HiFive1 Board! SiFive is changing the way industry builds silicon. Want to help democratize access to custom, state-of-art chips? Want to enable startups, companies, inventors, and makers like to find whole new range of applications? Enjoy working with really, really, smart people? San Francisco, California. San Francisco, California. San Francisco, California. Do you enjoy both hardware engineering and software engineering? San Francisco, California. The ideal candid...
antmicro.se
Antmicro - Blog
http://www.antmicro.se/Blog
July 12th, 2016. Antmicro’s smart MCU GUI library at Arduino Developer Summit. Antmicro’s smart GUI library for contained MCU devices has been drawing quite some attention recently. Following last year’s presentation at Designers of Things. In San Jose, USA, a stand of its own at Nuremberg’s Embedded World, Germany, later in 2016, and now an invitation to participate in the first Arduino Developer Summit – the library is making a strong appearance in the MCU space. On the event’s second day, Michael gave...
scala.zeef.com
Scala by Ivano Pagano | ZEEF
https://scala.zeef.com/index.xhtml
Scala is a modern multi-paradigm programming language designed to express common programming patterns in a concise, elegant, and type-safe way. It smoothly integrates features of object-oriented and functional languages. I’m an experienced java programmer and functional enthusiast exploring the possibilities offered by the versatile scala platform. Rome, Italy, Software Developer, Physics. Published 2 years ago. Updated 3 hours ago. The Scala Programming Language :. Performance and Optimization Libs.
chess.eecs.berkeley.edu
Precision Timed (PRET) Machines
https://chess.eecs.berkeley.edu/pret
Precision Timed (PRET) Machines. The goal of this project is to reintroduce timing predictability and repeatability by judiciously adopting architectural optimization techniques to deliver performance enhancements without sacrificing timing predictability and repeatability. Our approach includes extending the instruction-set architectures (ISA) with control over execution time. We have demonstrated that timing predictability and repeatability are not at odds with performance. PRET provides a starting poi...
maltanar.blogspot.com
maltanar's scribbles: AXI interfacing with Chisel
http://maltanar.blogspot.com/2014/11/axi-interfacing-with-chisel.html
Tuesday, November 25, 2014. AXI interfacing with Chisel. I recently started using Chisel. A hardware construction language from UC Berkeley implemented as a Scala DSL. Although it still has some rough edges, it's definitely usable and I really like how it can map the same description into Verilog or a cycle-accurate C simulation. I'm currently working on making hardware accelerators irregular applications (like graph traversal and sparse matrix operations - oh wait, we can do one with the other. It is wo...
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