indianmicroprocessor.blogspot.com

Indian Microprocessor

Saturday, July 24, 2010. OpenSPARC T1 and T2 Processor Implementation. As discussed previously, OpenSPARC gives preference to parallel computation rather than long pipelined instructions. Here is a diagram to summarize the concept. Most of the time, the processor will be stalled waiting on the memory or I/O operations. OpenSPARC T1 OVERVIEW AND COMPONENTS. OpenSPARC T1 Physical Core. Each core has support for 4 threads. They have a register file per strand. Each register file has 8 register windo...Switc...

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Saturday, July 24, 2010. OpenSPARC T1 and T2 Processor Implementation. As discussed previously, OpenSPARC gives preference to parallel computation rather than long pipelined instructions. Here is a diagram to summarize the concept. Most of the time, the processor will be stalled waiting on the memory or I/O operations. OpenSPARC T1 OVERVIEW AND COMPONENTS. OpenSPARC T1 Physical Core. Each core has support for 4 threads. They have a register file per strand. Each register file has 8 register windo...Switc...

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1 indian microprocessor

2 overview

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4 1 fetch

5 2 switch

6 3 decode

7 4 execute

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Indian Microprocessor | indianmicroprocessor.blogspot.com Reviews

https://indianmicroprocessor.blogspot.com

Saturday, July 24, 2010. OpenSPARC T1 and T2 Processor Implementation. As discussed previously, OpenSPARC gives preference to parallel computation rather than long pipelined instructions. Here is a diagram to summarize the concept. Most of the time, the processor will be stalled waiting on the memory or I/O operations. OpenSPARC T1 OVERVIEW AND COMPONENTS. OpenSPARC T1 Physical Core. Each core has support for 4 threads. They have a register file per strand. Each register file has 8 register windo...Switc...

INTERNAL PAGES

indianmicroprocessor.blogspot.com

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Indian Microprocessor: May 2010

http://indianmicroprocessor.blogspot.com/2010_05_01_archive.html

Sunday, May 30, 2010. The OpenSPARC T1 design is based on theUltraSPARC Architecture 2005, and OpenSPARC T2 is based on the UltraSPARC Architecture 2007. THE ULTRA SPARC ARCHITECTURE. Here I will be listing out a few of the important architectural features of UltraSPARC. Hardware Trap Stack: A hardware trap stack is provided to allow nested traps. It contains all of the machine state necessary to return to the previous trap level. Extended Instruction Set: It includes many instruction set extensions.

2

Indian Microprocessor: Ideas by Mr. Ashish

http://indianmicroprocessor.blogspot.com/2010/05/ideas-by-mr-ashish.html

Tuesday, May 18, 2010. Ideas by Mr. Ashish. Getting Started with OpenSPARC. Read Mr. Ashish's Blog on OpenSPARC Internals . http:/ fpga.ashishbanerjee.com/opensparc. This should give you an overview of OpenSPARC design. Synthesize an OpenSPARC core into an FPGA. The steps are detailed in OpenSPARC Internals book, Chapter 6. See the OpenSPARC T1 FPGA Video here: http:/ www.youtube.com/watch? Short Term Projects (BTech Level):. Extract NIU (Network Interface Unit) and synthesize it on a FPGA.

3

Indian Microprocessor: July 2010

http://indianmicroprocessor.blogspot.com/2010_07_01_archive.html

Saturday, July 24, 2010. OpenSPARC T1 and T2 Processor Implementation. As discussed previously, OpenSPARC gives preference to parallel computation rather than long pipelined instructions. Here is a diagram to summarize the concept. Most of the time, the processor will be stalled waiting on the memory or I/O operations. OpenSPARC T1 OVERVIEW AND COMPONENTS. OpenSPARC T1 Physical Core. Each core has support for 4 threads. They have a register file per strand. Each register file has 8 register windo...Switc...

4

Indian Microprocessor: Architecture Overview

http://indianmicroprocessor.blogspot.com/2010/05/architecture-overview.html

Sunday, May 30, 2010. The OpenSPARC T1 design is based on theUltraSPARC Architecture 2005, and OpenSPARC T2 is based on the UltraSPARC Architecture 2007. THE ULTRA SPARC ARCHITECTURE. Here I will be listing out a few of the important architectural features of UltraSPARC. Hardware Trap Stack: A hardware trap stack is provided to allow nested traps. It contains all of the machine state necessary to return to the previous trap level. Extended Instruction Set: It includes many instruction set extensions.

5

Indian Microprocessor: Synthesis of S1 core (Simply RISC)

http://indianmicroprocessor.blogspot.com/2010/05/synthesis-of-s1-core-simply-risc.html

Tuesday, May 18, 2010. Synthesis of S1 core (Simply RISC). We decided to get working on synthesizing S1 core of Simply RISC. These were the steps I followed:. 1 Install icarus-verilog from synaptic manager. 2 Extract http:/ www.srisc.com/download/s1 core.tar.gz. 3 Read the specs http:/ www.srisc.com/download/simplyrisc-s1-0.1.pdf. Went to the folder in which s1 core was extracted. In sourceme file made the following updation: export S1 ROOT= /home/aditya/SimplyRISC/s1 core. It is in errorlog 1. Http:/ os...

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indianmicroprocessor.blogspot.com

Indian Microprocessor

Saturday, July 24, 2010. OpenSPARC T1 and T2 Processor Implementation. As discussed previously, OpenSPARC gives preference to parallel computation rather than long pipelined instructions. Here is a diagram to summarize the concept. Most of the time, the processor will be stalled waiting on the memory or I/O operations. OpenSPARC T1 OVERVIEW AND COMPONENTS. OpenSPARC T1 Physical Core. Each core has support for 4 threads. They have a register file per strand. Each register file has 8 register windo...Switc...

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