j-core.org

J-core Open Processor

IRC channel #j-core on freenode. J-core is a clean-room open source processor and SOC design using the SuperH instruction set. Implemented in VHDL and available royalty and patent free under a BSD license. The rest of this page explains how to build the processor's FPGA bitstream and install it on a cheap (about $50) FPGA board, then how to build, install, and boot Linux to a shell prompt with serial console. Mimas v2 FPGA board. Or build the processor yourself from source). Into the board (via USB).

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J-core Open Processor | j-core.org Reviews

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IRC channel #j-core on freenode. J-core is a clean-room open source processor and SOC design using the SuperH instruction set. Implemented in VHDL and available royalty and patent free under a BSD license. The rest of this page explains how to build the processor's FPGA bitstream and install it on a cheap (about $50) FPGA board, then how to build, install, and boot Linux to a shell prompt with serial console. Mimas v2 FPGA board. Or build the processor yourself from source). Into the board (via USB).

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4 what is it

5 news

6 roadmap

7 talks

8 files

9 downloads

10 bitstream compiler

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J-core Open Processor | j-core.org Reviews

https://j-core.org

IRC channel #j-core on freenode. J-core is a clean-room open source processor and SOC design using the SuperH instruction set. Implemented in VHDL and available royalty and patent free under a BSD license. The rest of this page explains how to build the processor's FPGA bitstream and install it on a cheap (about $50) FPGA board, then how to build, install, and boot Linux to a shell prompt with serial console. Mimas v2 FPGA board. Or build the processor yourself from source). Into the board (via USB).

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lists.j-core.org Mailing Lists

Listsj-core.org Mailing Lists. Below is a listing of all the public mailing lists on lists.j-core.org. Click on a list name to get more information about the list, or to subscribe, unsubscribe, and change the preferences on your subscription. To visit the general information page for an unadvertised list, open a URL similar to this one, but with a '/' and the list name appended. List administrators, you can visit the list admin overview page. To find the management interface for your list.

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j-core.org

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J-core Open Processor

http://www.j-core.org/index.html

IRC channel #j-core on freenode. J-core is a clean-room open source processor and SOC design using the SuperH instruction set. Implemented in VHDL and available royalty and patent free under a BSD license. The rest of this page explains how to build the processor's FPGA bitstream and install it on a cheap (about $50) FPGA board, then how to build, install, and boot Linux to a shell prompt with serial console. Mimas v2 FPGA board. Or build the processor yourself from source). Into the board (via USB).

3

J-core Roadmap

http://www.j-core.org/roadmap.html

IRC channel #j-core on freenode. J-core processor development started in 2012 with the goal of implementing processors compatible with the existing SuperH instruction set, to be released as relevant patents expired. The original idea is that j1/j2/j3/j4 processors would support the corresponding SuperH sh1/sh2/sh3/sh4 instructions. This roadmap goes through sh4 compatibility, then diverges sharply. All the historical technology we're examining (sh1, sh2, sh3, and sh4) was developed in-house by Hitachi.

4

J-core Presentations

http://www.j-core.org/talks

IRC channel #j-core on freenode. Embedded Linux Conference 2016. The talk Building a CPU from Scratch: jcore Design Wakthrough. Has video is on youtube. And here are the slides. Linux Jamboree #54 (September 2015). We went back to Linux Jamboree ( the 1pm timeslot. To give an open processor tutorial where we gave away a dozen Numato Mimas v2 boards to the audience, and as our panel description said:. The video is in two parts, the first. The Turtles All the Way. Linux Jamboree #52 (April 10, 2015).

5

J-core Open Processor

http://www.j-core.org/news.html

IRC channel #j-core on freenode. June 27, 2016. On merging vanilla kernel support and status of the Turtle Board. June 21, 2016. The J-core engineers got together in Austin, and Rob did a brief writeup. A thread about using J-core on Kintex 7. Led to an explanation of the memory fpga.vhd module. And later an explanation of the two instr bus types. June 12, 2016. Next up is trying to simulate J2 with NVC. Jeff also posted a diff of J1 against the J2 tree. June 10, 2016. June 5, 2016. On the way there.

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Debian -- Ports

http://www.debian.org/ports

List of official ports. List of other ports. As most of you know, Linux. Is just a kernel. And, for a long time, the Linux kernel ran only on the Intel x86 series of machines, from the 386 up. Debian is an operating system (OS), not a kernel (actually, it is more than an OS since it includes thousands of application programs). Accordingly, while most Debian ports are based on Linux, there also are ports based on the FreeBSD, NetBSD and Hurd kernels. List of official ports. Hard Float ABI ARM. A lot of mo...

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IRC channel #j-core on freenode. J-core is a clean-room open source processor and SOC design using the SuperH instruction set. Implemented in VHDL and available royalty and patent free under a BSD license. The rest of this page explains how to build the processor's FPGA bitstream and install it on a cheap (about $50) FPGA board, then how to build, install, and boot Linux to a shell prompt with serial console. Mimas v2 FPGA board. Or build the processor yourself from source). Into the board (via USB).

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