jimmy10001.blogspot.com

VERILOG物語

Module arith1 ();. Reg [3:0] a,b;. Wire [4:0] sum,diff1,diff2,neg;. Assign sum = a b;. Assign diff1 = a-b;. Assign diff2 = b-a;. Assign neg =-a;. 5 a=7;b=3;. Display("t sim a b a b a-b b-a -a");. Monitor ($time,"%d %d %d %d %d %d",a,b,sum,diff1,diff2,neg);. Monitor ($time, "%b %b %b %b %b %b",a,b,sum,diff1,diff2,neg);. Posted by 照片非本人 at 4:56 下午. Module add rca 4(sum,c out,a,b,c in);output [3:0] sum;output c out;input [3:0] a,b;input c in;wire c out,c in4,c in3,c in2;add full G1(sum[0],c in2,a[0],b[0],c ...

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VERILOG物語 | jimmy10001.blogspot.com Reviews

<META> DESCRIPTION

Module arith1 ();. Reg [3:0] a,b;. Wire [4:0] sum,diff1,diff2,neg;. Assign sum = a b;. Assign diff1 = a-b;. Assign diff2 = b-a;. Assign neg =-a;. 5 a=7;b=3;. Display(t sim a b a b a-b b-a -a);. Monitor ($time,%d %d %d %d %d %d,a,b,sum,diff1,diff2,neg);. Monitor ($time, %b %b %b %b %b %b,a,b,sum,diff1,diff2,neg);. Posted by 照片非本人 at 4:56 下午. Module add rca 4(sum,c out,a,b,c in);output [3:0] sum;output c out;input [3:0] a,b;input c in;wire c out,c in4,c in3,c in2;add full G1(sum[0],c in2,a[0],b[0],c ...

<META> KEYWORDS

1 verilog物語

2 這是一場有關於verilog與jimmy之間轟轟烈烈的感情故事

3 arith1

4 initial

5 begin

6 10 $monitoroff;

7 endmodule

8 0 comments

9 add rca 4

10 initial begin

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verilog物語,這是一場有關於verilog與jimmy之間轟轟烈烈的感情故事,arith1,initial,begin,10 $monitoroff;,endmodule,0 comments,add rca 4,initial begin,test nand latch 1,module tnl1;,compare 2 str,not w6 a1 ;,not w7 a0 ;,上了這麼久的verilog雖然會打程式但是還是不會分析跑出來的圖是否正確,c in=0;,specify,關於我自己

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VERILOG物語 | jimmy10001.blogspot.com Reviews

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Module arith1 ();. Reg [3:0] a,b;. Wire [4:0] sum,diff1,diff2,neg;. Assign sum = a b;. Assign diff1 = a-b;. Assign diff2 = b-a;. Assign neg =-a;. 5 a=7;b=3;. Display("t sim a b a b a-b b-a -a");. Monitor ($time,"%d %d %d %d %d %d",a,b,sum,diff1,diff2,neg);. Monitor ($time, "%b %b %b %b %b %b",a,b,sum,diff1,diff2,neg);. Posted by 照片非本人 at 4:56 下午. Module add rca 4(sum,c out,a,b,c in);output [3:0] sum;output c out;input [3:0] a,b;input c in;wire c out,c in4,c in3,c in2;add full G1(sum[0],c in2,a[0],b[0],c ...

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jimmy10001.blogspot.com

1

VERILOG物語: 04/14/06

http://jimmy10001.blogspot.com/2006_04_14_archive.html

Module add full ;. Reg a,b,c in;. Wire sum,c out;. Wire w1,w2,w3;. J1 M1(w1,w2,a,b);. J1 M2(sum,w3,w1,c in);. Or(c out,w2,w3);. Always#160 c in= c in;. Always#40 a= a;. Always#80 b= b;. Module J1 (sum,c out,a,b);. Input a,b;. Output sum,c out;. Xor(sum,a,b);. And(c out,a,b);. Posted by 照片非本人 at 5:46 下午. 29031;片非本人. Cell-based implementation of a half adder.

2

VERILOG物語: 03/03/06

http://jimmy10001.blogspot.com/2006_03_03_archive.html

Http:/ residence.educities.edu.tw/oldfriend/page54.htm. Posted by 照片非本人 at 9:50 下午. Http:/ www.dyu.edu.tw/ cschen/CODA/doc/syncad.doc. Http:/ www.dyu.edu.tw/ cschen/Verilog%20Computer%20Design/SynaptiCAD.exe. Posted by 照片非本人 at 9:42 下午. 儲存檔名為 " .v ". 在 Project / Add File(s) 開啟檔案. Posted by 照片非本人 at 9:13 下午. Posted by 照片非本人 at 4:25 下午. 29031;片非本人. Cell-based implementation of a half adder.

3

VERILOG物語: cell-based implementation of a half adder

http://jimmy10001.blogspot.com/2006/04/cell-based-implementation-of-half.html

Cell-based implementation of a half adder. 雖然看不太清楚 , 但是還是看的出delay. Module add half ;. Wire sum,c out;. Wire c bar;. Xorf201 G1(sum,a,b);. Nanf201 G2(c bar,a,b);. Invf101 G3(c out,c bar);. Always#40 a= a;. Always#80 b= b;. Module nanf201 (c bar,a,b);. Input a,b;. Output c bar;. Nand (c bar,a,b);. Tpd 0 1 = 1.13:3.09:7.75,. Tpd 1 0 = 0.93:2.50:7.34;. A = c bar)=(tpd 0 1,tpd 1 0);. B = c bar)=(tpd 0 1,tpd 1 0);. Module xorf201 (sum,a,b);. Input a,b;. Xor (sum,a,b);. Tpd 0 1 = 1.13:3.09:7.75,. Input c bar;.

4

VERILOG物語: test-nand-latch-1

http://jimmy10001.blogspot.com/2006/05/test-nand-latch-1.html

Wire q,qb;. NL1 xxxz (q,qb,p,c);. Monitor($time,"p=%b c=%b q=%b qb=%b",p,c,q,qb);. 10 p =0; c=1;. 10 p =0; $stop;. Module NL1(q,qb,p,c);. Output q,qb;. Input p,c;. Nand g1(q,p,qb);. Nand g2(qb,c,q);. Posted by 照片非本人 at 5:25 下午. 29031;片非本人. Cell-based implementation of a half adder. C 程式(吊橋). 21322;加器.

5

VERILOG物語: add_rca_16

http://jimmy10001.blogspot.com/2006/05/addrca16.html

Module adder 16bit;. Reg [15:0] a,b;. Reg c in;. Wire[15:0] sum ;. Wire c out;. A[0]=0;a[1]=0;a[2]=0;a[3]=0;a[4]=0;a[5]=0;a[6]=0;a[7]=0;a[8]=0;a[9]=0;a[10]=0;a[11]=0;a[12]=0;a[13]=0;a[14]=0;a[15]=0;. B[0]=0;b[1]=0;b[2]=0;b[3]=0;b[4]=0;b[5]=0;b[6]=0;b[7]=0;b[8]=0;b[9]=0;b[10]=0;b[11]=0;b[12]=0;b[13]=0;b[14]=0;b[15]=0;. Always #5 a[0]= a[0];. Always #5 a[8]= a[8];. Always #10 a[1]= a[1];. Always #10 a[9]= a[9];. Always #15 a[2]= a[2];. Always #15 a[10]= a[10];. Always #20 a[3]= a[3];. Always #25 a[4]= a[4];.

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VERILOG物語

Module arith1 ();. Reg [3:0] a,b;. Wire [4:0] sum,diff1,diff2,neg;. Assign sum = a b;. Assign diff1 = a-b;. Assign diff2 = b-a;. Assign neg =-a;. 5 a=7;b=3;. Display("t sim a b a b a-b b-a -a");. Monitor ($time,"%d %d %d %d %d %d",a,b,sum,diff1,diff2,neg);. Monitor ($time, "%b %b %b %b %b %b",a,b,sum,diff1,diff2,neg);. Posted by 照片非本人 at 4:56 下午. Module add rca 4(sum,c out,a,b,c in);output [3:0] sum;output c out;input [3:0] a,b;input c in;wire c out,c in4,c in3,c in2;add full G1(sum[0],c in2,a[0],b[0],c ...

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