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mp3xu4: 計算機設計
http://lillian2714.blogspot.com/2007/03/blog-post.html
今天上課初步認識課程中會用到的工具軟體SynaptiCAD,也將範例做了些試驗,因為之前都沒修過老師的課,對於軟體的使用並不了解,相信在使用幾次後就會熟練多了! 訂閱： 張貼留言 (Atom).
mp3xu4: 第一階段;乘法機之行為模式設計考試
http://lillian2714.blogspot.com/2007/05/blog-post.html
Define NUM STATE BITS 3. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Posedge sysclk) enter new state(`IDLE);. Ready = 1;. Posedge sysclk) enter new state(`INIT);. Posedge sysclk) enter new state(`INIT1);. Posedge sysclk) enter new state(`COMPUTE1);. Posedge sysclk) enter new state(`COMPUTE2);.
計算機設計: 3/19 第一階段測試結果
http://hindo0149.blogspot.com/2007/03/319.html
Http:/ www.dyu.edu.tw/ f9203818/test1/. 訂閱： 張貼留言 (Atom).
計算機設計: 2007/04/08第二階段測試
http://hindo0149.blogspot.com/2007/04/20070408.html
更改slow div arch的內容.alu主要使用到的功能為r1=r1-1;. 主要的加法交給counter register 來執行r2=r2 y;. 因為將加法放置在counter register來執行,所以執行的時間變長了,這是需要改進的地方. Define NUM STATE BITS 1. Module next state logic(next state,. Ldr1,incr2,clrr2,ldr3,. Muxctrl,aluctrl, ready,. Present state, r1gey, pb);. Output next state,ldr1,incr2,clrr2,ldr3,muxctrl,aluctrl,ready;. Input present state, r1gey, pb;. Reg [`NUM STATE BITS-1:0] next state;. Reg ldr1,incr2,clrr2,ldr3,muxctrl,ready;. Reg [5:0] aluctrl;. Wire [`NUM STATE BITS-1:0] present state;.
mp3xu4: 四月 2007
http://lillian2714.blogspot.com/2007_04_01_archive.html
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mp3xu4: 五月 2007
http://lillian2714.blogspot.com/2007_05_01_archive.html
Define NUM STATE BITS 3. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Posedge sysclk) enter new state(`IDLE);. Ready = 1;. Posedge sysclk) enter new state(`INIT);. Posedge sysclk) enter new state(`INIT1);. Posedge sysclk) enter new state(`COMPUTE1);. Posedge sysclk) enter new state(`COMPUTE2);.
mp3xu4: 三月 2007
http://lillian2714.blogspot.com/2007_03_01_archive.html
除法機 修改為 乘法機 完成圖. 今天上課初步認識課程中會用到的工具軟體SynaptiCAD,也將範例做了些試驗,因為之前都沒修過老師的課,對於軟體的使用並不了解,相信在使用幾次後就會熟練多了! 訂閱： 文章 (Atom).
mp3xu4: 第二階段 除法機混合模式設計"模擬圖"
http://lillian2714.blogspot.com/2007/04/blog-post.html
訂閱： 張貼留言 (Atom).
計算機設計: 五月 2007
http://hindo0149.blogspot.com/2007_05_01_archive.html
Http:/ www.dyu.edu.tw/ f9203818/test2/. 更改slow div arch的內容，alu主要使用到的功能為r1=r1＋ｘ;. 主要的加法交給counter register來執行r2=r2－１，將comparator與y的比較改成跟１的比較，另外再多加一條線r2k用來控制counter register的下數。以下為ASM圖. Define NUM STATE BITS 1. Module next state logic(next state,. Ldr1,incr2,clrr2,ldr3,. Muxctrl,aluctrl, ready,. Present state, r1gey, pb,r2k);. Output next state,ldr1,incr2,clrr2,ldr3,muxctrl,aluctrl,ready,r2k;. Input present state, r1gey, pb;. Reg [`NUM STATE BITS-1:0] next state;. Reg ldr1,incr2,clrr2,ldr3,muxctrl,ready,r2k;.
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