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HDL Verification with Maia - Welcome! | maia-eda.net Reviews
https://maia-eda.net
HDL verification with Maia
maia-eda.net
HDL Verification with Maia - Welcome!
http://www.maia-eda.net/index.php
Monday, 29 August 2016. A first Maia program. Is Maia for me? HDL coding styles for synthesis: VHDL and Verilog code examples, together with Maia testbenches. Maia is a low-level verification language. Its purpose is to verify Verilog and VHDL modules, by using simple 'vectors' to drive the module inputs, and to check the resulting outputs. Maia code is simple and intuitive, and lets you trivially check HDL modules, without writing. You can download a Maia compiler (. Section contains a number of simple ...
HDL Verification with Maia
http://www.maia-eda.net/index.php?option=com_joomap&Itemid=142
Monday, 29 August 2016. A first Maia program. Is Maia for me? 2008-2010 Maia EDA Ltd.
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