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DDR3 controller - from scratch

DDR3 controller - from scratch. Monday, August 16, 2010. Write leveling - in more detail. Inconsistencies in DDR3 specifications (JEDEC and Micron):. Under the topic of 'Write Leveling Procedure':. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied. Also for tWLS and tWLH, look at the JEDEC waveform. It's obvious what they mean, but it's shown very badly in the Micron figure. Here is a version that uses wl.v - a module that takes care of write leveling. I am now detecting the separat...Outpu...

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DDR3 controller - from scratch | myddr3controller.blogspot.com Reviews

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DDR3 controller - from scratch. Monday, August 16, 2010. Write leveling - in more detail. Inconsistencies in DDR3 specifications (JEDEC and Micron):. Under the topic of 'Write Leveling Procedure':. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied. Also for tWLS and tWLH, look at the JEDEC waveform. It's obvious what they mean, but it's shown very badly in the Micron figure. Here is a version that uses wl.v - a module that takes care of write leveling. I am now detecting the separat...Outpu...

<META> KEYWORDS

1 module wl

2 input start

3 if ddr3 rst begin

4 end else begin

5 case dqs state

6 dqs high begin

7 endcase

8 dqs low begin

9 if iodelay rst begin

10 case state

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module wl,input start,if ddr3 rst begin,end else begin,case dqs state,dqs high begin,endcase,dqs low begin,if iodelay rst begin,case state,increment 0 begin,go 0 begin,increment 1 begin,go 1 begin,done begin,idle begin,check 0 begin,else,if wait 0 9,topv

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DDR3 controller - from scratch | myddr3controller.blogspot.com Reviews

https://myddr3controller.blogspot.com

DDR3 controller - from scratch. Monday, August 16, 2010. Write leveling - in more detail. Inconsistencies in DDR3 specifications (JEDEC and Micron):. Under the topic of 'Write Leveling Procedure':. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied. Also for tWLS and tWLH, look at the JEDEC waveform. It's obvious what they mean, but it's shown very badly in the Micron figure. Here is a version that uses wl.v - a module that takes care of write leveling. I am now detecting the separat...Outpu...

INTERNAL PAGES

myddr3controller.blogspot.com

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DDR3 controller - from scratch: Write leveling - in more detail

http://myddr3controller.blogspot.com/2010/08/write-leveling-in-more-detail.html

DDR3 controller - from scratch. Monday, August 16, 2010. Write leveling - in more detail. Inconsistencies in DDR3 specifications (JEDEC and Micron):. Under the topic of 'Write Leveling Procedure':. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied. Also for tWLS and tWLH, look at the JEDEC waveform. It's obvious what they mean, but it's shown very badly in the Micron figure. Here is a version that uses wl.v - a module that takes care of write leveling. I am now detecting the separat...Outpu...

2

DDR3 controller - from scratch: First steps

http://myddr3controller.blogspot.com/2010/08/first-steps.html

DDR3 controller - from scratch. Friday, August 6, 2010. The last time I played this little puzzle was with a Lattice FPGA and a DDR2 chip. Started by reading the Micron specification for the DDR2 chip, and then began writing. It was lots of fun, got the chip working, learned a huge amount in the process, and inevitably switched over to Lattice's hard-core DDR2 controller. See: http:/ ionipti.blogspot.com/2010/07/help-ddr3-odt-on-die-termination.html. Subscribe to: Post Comments (Atom).

3

DDR3 controller - from scratch: August 2010

http://myddr3controller.blogspot.com/2010_08_01_archive.html

DDR3 controller - from scratch. Monday, August 16, 2010. Write leveling - in more detail. Inconsistencies in DDR3 specifications (JEDEC and Micron):. Under the topic of 'Write Leveling Procedure':. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied. Also for tWLS and tWLH, look at the JEDEC waveform. It's obvious what they mean, but it's shown very badly in the Micron figure. Here is a version that uses wl.v - a module that takes care of write leveling. I am now detecting the separat...Outpu...

4

DDR3 controller - from scratch: Initialization

http://myddr3controller.blogspot.com/2010/08/initialization.html

DDR3 controller - from scratch. Friday, August 6, 2010. Following Micron's initialization procedure is fairly simple. Of course you do have to know whether you are doing it right. When I play with a new device, I like to see it respond as soon as possible. I created the initialization state machine, and put it into write leveling mode. Instantiate an MMCM ADV to create a 300 MHz phase 0, and a 300 MHz phase -90 from the 200 MHz system clock. Instantiate one IDELAYCTRL with a 200 MHz clock. Input SYSCLK N,.

5

DDR3 controller - from scratch: Aligning DQSs - Add ODDR at IOs

http://myddr3controller.blogspot.com/2010/08/aligning-dqss-add-oddr-at-ios.html

DDR3 controller - from scratch. Tuesday, August 10, 2010. Aligning DQSs - Add ODDR at IOs. I want to start seeing more appropriate write leveling data. Currently the write leveling is giving coherent results, but they are unaligned. I see that is because of the routing per each DQS from their FF. Now I've added an ODDR to put all DQSs at their respective IOs. Xilinx's tools require that the ODDR sit before the IODELAY. Here is the relevant code in top.v:. Genvar dqs i;. Wire dqs out oddr;.

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DDR3 controller - from scratch

DDR3 controller - from scratch. Monday, August 16, 2010. Write leveling - in more detail. Inconsistencies in DDR3 specifications (JEDEC and Micron):. Under the topic of 'Write Leveling Procedure':. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied. Also for tWLS and tWLH, look at the JEDEC waveform. It's obvious what they mean, but it's shown very badly in the Micron figure. Here is a version that uses wl.v - a module that takes care of write leveling. I am now detecting the separat...Outpu...

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