nl.jandecaluwe.com
Opinie
http://nl.jandecaluwe.com/opinie
Sigasi / Jan on HDL Design. Succes is een kwestie van hard willen. Ook bij Unia vinden ze de antidiscriminatiewet maar niets. Logica als leidraad (Waarom Rik Torfs ongelijk heeft). Het gevaarlijke bedrog met de armoedenorm. Een pleidooi voor de vrijheid (ook om te discrimineren). De heilloze perceptie-politiek van Paul De Grauwe. Marc Coucke: 2.07 miljard winst, 0.62 miljard belasting. De Leuvense Kotbaas, een nieuw fiscaal fenomeen. Het verschil tussen Marc Coucke en LuxLeaks. Ontgoocheld in de N-VA.
nl.jandecaluwe.com
n-va
http://nl.jandecaluwe.com/tag/n-va
Sigasi / Jan on HDL Design. Ontgoocheld in de N-VA.
public.ska.ac.za
Software - SKA SA Public
http://public.ska.ac.za/software
KAT-7 Images and Data. KAT-7 Science Verification Programme. MeerKAT Spec and Schedule. This page lists software alphabetically that SKA SA is involved in and is publicly available. Many are open-source projects which we either lead or contribute to, many through the CASPER. Collaboration (our DBE team, in particular). A number of these are consolidated at the SKA SA presence on github: http:/ github.com/ska-sa. And additional CASPER software repositories are hosted at https:/ github.com/casper-astro.
mgaitan.github.io
Charlas y cursos | tin_nqn
http://mgaitan.github.io/charlas.html
Tin nqn me.geek.post(). Diez consejos para un mejor software (de) científico(s). He lidiado (y aprendido) con el código escrito por científicos. Mentes brillantes, expertas en su campo de investigación, tienen como herramienta principal un lenguaje de programación cuyo aprendizaje ha sido informal, de fuentes erróneas o anticuadas, siguiendo ejemplos llenos de vicios y malas prácticas transmitidas de generación en generación. Universidad Nacional del Sur, Bahía Blanca, Argentina. 22 de octubre de 2014.
potential.ventures
Cocotb
http://potential.ventures/cocotb
Coroutine Co-simulation Test Bench. Download this project as a .zip file. Download this project as a tar.gz file. Is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. V04 Release now available. Get involved: Raise a bug / request an enhancement. Requires a GitHub account). Get in contact: E-mail us. Follow us on Twitter: @PVCocotb. Licensed under the BSD license and compatible with the Icarus Verilog. Why verify in Python? Writing Python is fast. Seeks to displace...
c-cam.be
Careers
http://www.c-cam.be/Careers.html
Electronic Systems Design Engineer. Update August 30th, 2015. Designer of Scientific and Industrial Cameras. The work consists of an interesting mix of design and development of new camera and camera-related products and also involvement in the execution of projects and applications with third-parties. Typical projects range from industrial vision, monitoring and inspection, to aerospace applications. Preferably some years of experience in design and debugging of digital electronic systems. Created at Ta...
dev.myhdl.org
Info
http://dev.myhdl.org/info.html
Last modified: 17-Jul-2015 by Jan Decaluwe. The dev.myhdl.org. Website documents all aspects of the development process of the MyHDL project. MyHDL is a Python library to use Python as a. The main project website is here. This website is developed collaboratively by the MyHDL development community. It is developed using the Urubu. Software. Read more ». The theme of this website uses the Bootstrap. Framework. It is based on the Flatly. Theme, provided by Bootswatch. Content licensed under the CC-BY-SA.
dsprelated.com
A Fixed-Point Introduction by Example - Christopher Felton
https://www.dsprelated.com/showarticle/139.php
A Fixed-Point Introduction by Example. April 25, 2011. The finite-word representation of fractional numbers is known as fixed-point. Fixed-point is an interpretation of a 2's compliment number usually signed but not limited to sign representation. It extends our finite-word length from a finite set of integers to a finite set of rational real numbers [1]. A fixed-point representation of a number consists of integer and fractional components. The bit length is defined as:. Is the integer word length, FWL.
jandecaluwe.com
About me
http://www.jandecaluwe.com/about-me.html
I am an electronic engineering professional with an entrepreneurial spirit. I have a strong interest in electronic design, methodology, electronic design automation (EDA), and EDA tool development. I have participated in a wide range of successful digital ASIC, mixed-signal ASIC and FPGA design projects for telecom, DSP, sensor, and image processing applications. I have in-depth experience in methodologies based on VHDL, Verilog, SystemVerilog, SystemC, and MyHDL. I have co-founded Easics. Is my latest o...
jandecaluwe.com
My sites
http://www.jandecaluwe.com/projects
Sigasi / Jan on HDL.
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