ROXJRJU.BLOGSPOT.COM

verilog

Module compare 2 str(a lt b,a gt b,a eq b,a,b);. Input [1:0] a,b;. Output a lt b,a gt b,a eq b;. Reg a lt b,a gt b,a eq b;. Always @(a or b). A lt b=0;. A gt b=0;. A eq b=0;. If(a= b) a eq b=1;. Else if(a b) a gt b=1;. Else a lt b=1;. Module system clock(clk);. PERIOD/2) clk= clk;. PERIOD/2) clk= clk;. If($time 1000) #(PERIOD-1) $stop;. Wire a1,a0,b1,b0;. Wire a lt b,a gt b,a eq b;. System clock #400 clk(a1);. System clock #200 clk(a0);. System clock #100 clk(b1);. System clock #50 clk(b0);. Wire y out;.

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verilog | roxjrju.blogspot.com Reviews

<META> DESCRIPTION

Module compare 2 str(a lt b,a gt b,a eq b,a,b);. Input [1:0] a,b;. Output a lt b,a gt b,a eq b;. Reg a lt b,a gt b,a eq b;. Always @(a or b). A lt b=0;. A gt b=0;. A eq b=0;. If(a= b) a eq b=1;. Else if(a b) a gt b=1;. Else a lt b=1;. Module system clock(clk);. PERIOD/2) clk= clk;. PERIOD/2) clk= clk;. If($time 1000) #(PERIOD-1) $stop;. Wire a1,a0,b1,b0;. Wire a lt b,a gt b,a eq b;. System clock #400 clk(a1);. System clock #200 clk(a0);. System clock #100 clk(b1);. System clock #50 clk(b0);. Wire y out;.

<META> KEYWORDS

1 skip to main

2 skip to sidebar

3 verilog

4 begin

5 endmodule

6 parameter period=100;

7 output clk;

8 reg clk;

9 initial

10 clk=0;

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skip to main,skip to sidebar,verilog,begin,endmodule,parameter period=100;,output clk;,reg clk;,initial,clk=0;,always,always @ posedge clk,module test;,張貼者：,roxjrju,沒有留言,module top;,always@ posedge clk,較舊的文章,網誌存檔,關於我自己,檢視我的完整簡介

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verilog | roxjrju.blogspot.com Reviews

https://roxjrju.blogspot.com

Module compare 2 str(a lt b,a gt b,a eq b,a,b);. Input [1:0] a,b;. Output a lt b,a gt b,a eq b;. Reg a lt b,a gt b,a eq b;. Always @(a or b). A lt b=0;. A gt b=0;. A eq b=0;. If(a= b) a eq b=1;. Else if(a b) a gt b=1;. Else a lt b=1;. Module system clock(clk);. PERIOD/2) clk= clk;. PERIOD/2) clk= clk;. If($time 1000) #(PERIOD-1) $stop;. Wire a1,a0,b1,b0;. Wire a lt b,a gt b,a eq b;. System clock #400 clk(a1);. System clock #200 clk(a0);. System clock #100 clk(b1);. System clock #50 clk(b0);. Wire y out;.

INTERNAL PAGES

roxjrju.blogspot.com

1

verilog: 10/06上課練習

http://roxjrju.blogspot.com/2008/10/1006.html

Design a verilog model of a half adder and erite a testbench to verify the designed verilog model . Module Add half (sum,c out,a,b);. Input a,b;. Output sum,c out;. Wire c out bar;. Xor (sum,a,b);. Nand(c out bar,a,b);. Not(c out,c out bar);. 訂閱：張貼留言 (Atom).

2

verilog: 10/13上課練習

http://roxjrju.blogspot.com/2008/10/1013.html

Wire a,b;. Wire sum,c out;. System clock #100 clock1(a);. System clock #50 clock2(b);. Add half AH1(sum,c out,a,b);. Module Add half(sum,c out, a, b);. Input a,b;. Output sum,c out;. Wire c out bar;. Xor(sum, a, b);. Nand(c out bar, a, b);. Not(c out,c out bar);. Module system clock(clk);. Parameter PERIOD = 100;. PERIOD/2) clk = clk;. PERIOD/2) clk = clk;. If($time 1000) #(PERIOD-1)$stop;. 訂閱：張貼留言 (Atom).

3

verilog: 10/13 Add_full

http://roxjrju.blogspot.com/2008/10/1013-addfull.html

Module Add full(sum,c out,a,b,c in);. Input a,b,c in;. Output sum c out;. Wire w1,w2,w3;. Add half M1(w1,w2,a,b);. Add half M2(sum,w3,w1,c in);. Or (c out,w2,w3);. 訂閱：張貼留言 (Atom).

4

verilog: 十二月 2008

http://roxjrju.blogspot.com/2008_12_01_archive.html

Module compare 2 str(a lt b,a gt b,a eq b,a,b);. Input [1:0] a,b;. Output a lt b,a gt b,a eq b;. Reg a lt b,a gt b,a eq b;. Always @(a or b). A lt b=0;. A gt b=0;. A eq b=0;. If(a= b) a eq b=1;. Else if(a b) a gt b=1;. Else a lt b=1;. Module system clock(clk);. PERIOD/2) clk= clk;. PERIOD/2) clk= clk;. If($time 1000) #(PERIOD-1) $stop;. Wire a1,a0,b1,b0;. Wire a lt b,a gt b,a eq b;. System clock #400 clk(a1);. System clock #200 clk(a0);. System clock #100 clk(b1);. System clock #50 clk(b0);.

5

verilog: 九月 2008

http://roxjrju.blogspot.com/2008_09_01_archive.html

Wire a,b;. System clock #100 clock1(a);. System clock #50 clock2(b);. Module system clock(clk);. Http:/ dyu9502.blogspot.com/. 訂閱：文章 (Atom).

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Module compare 2 str(a lt b,a gt b,a eq b,a,b);. Input [1:0] a,b;. Output a lt b,a gt b,a eq b;. Reg a lt b,a gt b,a eq b;. Always @(a or b). A lt b=0;. A gt b=0;. A eq b=0;. If(a= b) a eq b=1;. Else if(a b) a gt b=1;. Else a lt b=1;. Module system clock(clk);. PERIOD/2) clk= clk;. PERIOD/2) clk= clk;. If($time 1000) #(PERIOD-1) $stop;. Wire a1,a0,b1,b0;. Wire a lt b,a gt b,a eq b;. System clock #400 clk(a1);. System clock #200 clk(a0);. System clock #100 clk(b1);. System clock #50 clk(b0);. Wire y out;.

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