sctest.cse.ucsc.edu

SCTEST home page

ELCOME TO THE SCT. Group does research in testing, testability, and diagnosis of integrated circuits. Organizations that support our work. Faculty are Joel Ferguson. Undergrad elves are in need of replenishing. Distinguished alums (some of whom may return) are. Guests and collaborators are:. Publications, sorted by publication date. Or selected by topic:. Physical design for testability. An ATPG, DTPG, and fault simulation package. A testing visualization tool. PDFT scripts for Physical Design and Test.

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SCTEST home page | sctest.cse.ucsc.edu Reviews

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ELCOME TO THE SCT. Group does research in testing, testability, and diagnosis of integrated circuits. Organizations that support our work. Faculty are Joel Ferguson. Undergrad elves are in need of replenishing. Distinguished alums (some of whom may return) are. Guests and collaborators are:. Publications, sorted by publication date. Or selected by topic:. Physical design for testability. An ATPG, DTPG, and fault simulation package. A testing visualization tool. PDFT scripts for Physical Design and Test.

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SCTEST home page | sctest.cse.ucsc.edu Reviews

https://sctest.cse.ucsc.edu

ELCOME TO THE SCT. Group does research in testing, testability, and diagnosis of integrated circuits. Organizations that support our work. Faculty are Joel Ferguson. Undergrad elves are in need of replenishing. Distinguished alums (some of whom may return) are. Guests and collaborators are:. Publications, sorted by publication date. Or selected by topic:. Physical design for testability. An ATPG, DTPG, and fault simulation package. A testing visualization tool. PDFT scripts for Physical Design and Test.

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sctest.cse.ucsc.edu

1

Jianlin Yu's Homepage

http://sctest.cse.ucsc.edu/jianlin

Welcome to Jianlin Yu's homepage. Jianlin is a graduate student in the SCTest group. Jianlin works on statistical analysis of yield loss, and designing the process monitors for defect diagnosability. Jianlin also had worked on simulation and test generation of faults inside gates.

2

Publications

http://sctest.cse.ucsc.edu/papers/fa.html

Selected SCTest publications on diagnosis (sorted in reverse chronological order):. And F J. Ferguson. Diagnosing Realistic Bridging Faults with Single Stuck-At Information. IEEE Transactions on Computer-Aided Design. 255-268, March, 1998. Jayashree Saxena, and Kenneth Butler. Bridging Fault Diagnosis in the Absence of Physical Information. In Proceedings of the International Test Conference. 887-893, November 1997. Maximum Likelihood Estimation for Yield Analysis. Department of Computer Engineering.

3

Publications

http://sctest.cse.ucsc.edu/papers/pdft.html

Selected SCTest publications on pdft (sorted in reverse chronological order):. A Study on the Utility of using Expected Quality Level as a Design for Testability Metric. In Proceedings of the International Test Conference. 274-282, March 1998. And F J. Ferguson. Incorporating Physical Design-For-Test into Routing. In Proceedings of the International Test Conference. 685-693, November 1997. And F J. Ferguson. A Methodology for Characterizing Cell Testability. In Proceedings of the 15th VLSI Test Symposium.

4

Santa Cruz Testing Publications

http://sctest.cse.ucsc.edu/papers/publications.html

Publications sorted in reverse chronological order:. And F J. Ferguson. Diagnosing Realistic Bridging Faults with Single Stuck-At Information. IEEE Transactions on Computer-Aided Design. 255-268, March, 1998. A Study on the Utility of using Expected Quality Level as a Design for Testability Metric. In Proceedings of the 16th VLSI Test Symposium. 274-282, March 1998. Testing Bridging Faults in CMOS Integrated Circuits. Jayashree Saxena, and Kenneth Butler. 887-893, November 1997. And F J. Ferguson. Beyond...

5

Publications

http://sctest.cse.ucsc.edu/papers/fm.html

Selected SCTest publications on fault modeling (sorted in reverse chronological order):. And F J. Ferguson. Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. In Proceedings of the International Test Conference. 597-606, November 1997. Testing for Opens in Digital CMOS Circuits. Doctoral Thesis, University of California at Santa Cruz. Department of Computer Engineering. Charge-based fault simulation for CMOS network breaks. IEEE Transactions on Computer-Aided Design.

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Links - TEST PLAZA

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Asia and Pacific Regional TTTC, IEEE CS. Asian Test Symposia, IEEE. 10th Asian Test Symposium, ATS'01. 11th Asian Test Symposium, ATS'02. 12th Asian Test Symposium, ATS'03. 13th Asian Test Symposium, ATS'04. 14th Asian Test Symposium, ATS'05. 15th Asian Test Symposium, ATS'06. 16th Asian Test Symposium, ATS'07. 17th Asian Test Symposium, ATS'08. 18th Asian Test Symposium, ATS'09. 19th Asian Test Symposium, ATS'10. 1st Asian Test Symposium, ATS'92. 20th Asian Test Symposium, ATS'11. 9th Workshop on RTL an...

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SCTEST home page

ELCOME TO THE SCT. Group does research in testing, testability, and diagnosis of integrated circuits. Organizations that support our work. Faculty are Joel Ferguson. Undergrad elves are in need of replenishing. Distinguished alums (some of whom may return) are. Guests and collaborators are:. Publications, sorted by publication date. Or selected by topic:. Physical design for testability. An ATPG, DTPG, and fault simulation package. A testing visualization tool. PDFT scripts for Physical Design and Test.

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