apegate.roma1.infn.it
SHAPES project - APEWiki
http://apegate.roma1.infn.it/mediawiki/index.php/SHAPES_project
INFN Roma group in the SHAPES project. The Distributed Network Processor in the SHAPES Tile. A scalable architecture: the DNP and the interTile communication ports. One chip, multiple tiles. The SHAPES tile in a 3D lattice. The Distributed Network Processor: HW architecture. INFN Roma group in the SHAPES project. The INFN Roma group's contribution to the SHAPES. Project consist of a TLM-SystemC and a VHDL model of the DNP. The Distributed Network Processor in the SHAPES Tile. One chip, multiple tiles.
euretile.roma1.infn.it
CASTNESS 08 - Euretile
http://euretile.roma1.infn.it/mediawiki/index.php/CASTNESS_08
CASTNESS'08 Workshop and School. Computing Architectures and Sw Tools for Numerical Embedded Scalable Systems. 15th-18th January 2008 - Roma - Italy. The programme committe is composed of SHAPES and HARTES members. SHAPES: Ahmed Jerraya, Rainer Leupers, Pier Stanislao Paolucci, Frederic Rousseau, Lothar Thiele, Piero Vicini. HARTES: Piergiovanni Bazzana, Volker Hahn, Wayne Luk, Francesco Piazza, Remond Sautreau, Donatella Sciuto. SHAPES - http:/ www.shapes-p.org. HARTES - http:/ www.hartes.org. To downlo...
apegate.roma1.infn.it
APE - The Array Processor Experiment web site in Rome
http://apegate.roma1.infn.it/APE_OLD
APE - The Array Processor Experiment. Active since 1984, APE("ah-pei") is the collective name of several generations of massively parallel super-computers, optimized for Theoretical Physics simulations, mainly LGT Simulations. They are built on custom processors connected by a high bandwidth, low latency communication network. The APE machines are recognized as a leading platform for LQCD. A most demanding High Performance Computing (HPC) application. And Université Paris-Sud 11. Design, designing VLIW.
euretile.roma1.infn.it
CASTNESS 07 - Euretile
http://euretile.roma1.infn.it/mediawiki/index.php/CASTNESS_07
CASTNESS'07 Workshop and School. Computing Architectures and Sw Tools for Numerical Embedded Scalable Systems. 15th-17th January 2007 in Roma - Italy. Links to CASTNESS '07 flyer. Ahmed Jerraya, Rainer Leupers, Pier Stanislao Paolucci, Lothar Thiele, Piero Vicini. During CASTNESS'07 it will be also presented the INFN Petaflops Ape project proposal, which is assumed to start during 2007, allowing the actual exploitation onto a physically working peta-flops system. 08:40-09:00 - Luca Benini - Universita' d...
aether-ist.org
AETHER (Self-adaptive computing) - Welcome to the ÆTHER project website
http://www.aether-ist.org/home/index.htm
Access to teaching material from AMWAS. Final Project Review for the AETHER Project. Third Review for SARC and SHAPES. Welcome to the ÆTHER project website. ÆTHER is an IST-FET project funded under the 6. Framework programme (FP6). Selected under the fourth call in the. Advanced Computing Architecture (ACA). Initiative of the Future and Emerging Technologies (FET) programme, ÆTHER. Project started January 1. 2006 for a duration of 36 months. NEW: The Final Project Review of the AETHER Project. The second...
simonkuenzli.ch
Simon Künzli
http://www.simonkuenzli.ch/projects.html
The area of research I am interested in can be described as design space exploration. I have been (and still am) working on several aspects of design space exploration for embedded systems: performance analysis, modelling of applications and architectures, and multiobjective optimization. In the domain of embedded systems, I and my colleagues focus mainly on the design space exploration for network processors. Conversion-Tool to translate Moses-XML into SPIML and vice versa. To learn more about this tool.
