skyayu.blogspot.com

SkyAyu

星期五, 6月 09, 2006. Module test Add rca 4();. Reg [3:0] a,b;. Reg c in;. Wire [3:0] sum;. Wire c out;. Display($time, "c out=%b c in4=%b c in3=%b c in2=%b c in=%b,sum[0]=%b",. C out,M1.c in4,M1.c in3,M1.c in2,c in,sum[0]). 40 c in= c in;. Add rca 4 M1 (sum,c out,a,b,c in);. Module Add rca 4 (sum,c out,a,b,c in);. Output [3:0] sum;. Output c out;. Input [3:0] a,b;. Input c in;. Wire c out,c in4,c in3,c in2;. Add full G1 (sum[0],c in2,a[0],b[0],c in);. Add full G2 (sum[1],c in3,a[1],b[1],c in2);. Input a,b;.

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SkyAyu | skyayu.blogspot.com Reviews

<META> DESCRIPTION

星期五, 6月 09, 2006. Module test Add rca 4();. Reg [3:0] a,b;. Reg c in;. Wire [3:0] sum;. Wire c out;. Display($time, c out=%b c in4=%b c in3=%b c in2=%b c in=%b,sum[0]=%b,. C out,M1.c in4,M1.c in3,M1.c in2,c in,sum[0]). 40 c in= c in;. Add rca 4 M1 (sum,c out,a,b,c in);. Module Add rca 4 (sum,c out,a,b,c in);. Output [3:0] sum;. Output c out;. Input [3:0] a,b;. Input c in;. Wire c out,c in4,c in3,c in2;. Add full G1 (sum[0],c in2,a[0],b[0],c in);. Add full G2 (sum[1],c in3,a[1],b[1],c in2);. Input a,b;.

<META> KEYWORDS

1 skyayu

2 add rca 4

3 initial

4 begin

5 c in=0;

6 always

7 endmodule

8 這次的程式很困難大概做完了

9 訊號不知道有沒有給錯

10 0 comments

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skyayu,add rca 4,initial,begin,c in=0;,always,endmodule,這次的程式很困難大概做完了,訊號不知道有沒有給錯,0 comments,module top;,wire y1;,p75 nand latch,stop;,這次的程式碼課本有很多錯誤,修改了很多錯誤才成功,這次的程式讓我了解delay是如何運作,今天練習了比較器,對verilog也越來越熟悉了,flip flop,wire q;,data in=0;,clk=0;,set=1;,rst=0;

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SkyAyu | skyayu.blogspot.com Reviews

https://skyayu.blogspot.com

星期五, 6月 09, 2006. Module test Add rca 4();. Reg [3:0] a,b;. Reg c in;. Wire [3:0] sum;. Wire c out;. Display($time, "c out=%b c in4=%b c in3=%b c in2=%b c in=%b,sum[0]=%b",. C out,M1.c in4,M1.c in3,M1.c in2,c in,sum[0]). 40 c in= c in;. Add rca 4 M1 (sum,c out,a,b,c in);. Module Add rca 4 (sum,c out,a,b,c in);. Output [3:0] sum;. Output c out;. Input [3:0] a,b;. Input c in;. Wire c out,c in4,c in3,c in2;. Add full G1 (sum[0],c in2,a[0],b[0],c in);. Add full G2 (sum[1],c in3,a[1],b[1],c in2);. Input a,b;.

INTERNAL PAGES

skyayu.blogspot.com

1

SkyAyu: 四月 2006

http://skyayu.blogspot.com/2006_04_01_archive.html

星期五, 4月 28, 2006. Reg A1,B1;. Nanf201 G1(o,A1,B1);. 50 A1= A1;. 30 B1= B1;. Module nanf201(o,A1,B1);. Input A1,B1;. Nand(o,A1,B1);. Tpd 0 1=1.13:3.09:7.75,. Tpd 1 0=0.93:2.5:7.34;. A1= o)=(Tpd 0 1,Tpd 1 0);. B1= o)=(Tpd 0 1,Tpd 1 0);. Posted by 周益賢 at 5:12 下午. 星期五, 4月 14, 2006. Reg a,b,c in;. Wire sum,c out,w1,w2,w3;. Add half M1(w1,w2,a,b);. Add half M2(sum,w3,w1,c in);. Or(c out,w2,w3);. 200 c in= c in;. 100 b= b;. Emodule Add half(sum,c out,a,b);. Input a,b;. Output sum,c out;. Xor (sum,a,b);.

2

SkyAyu: 三月 2006

http://skyayu.blogspot.com/2006_03_01_archive.html

星期五, 3月 31, 2006. Posted by 周益賢 at 5:49 下午. 星期五, 3月 24, 2006. Reg data in,clk;. Flip flop m1(q,data in,clk,rst);. 100 data in= data in;. 30 clk= clk;. Module Flip flop (q,data in,clk,rst);. Input data in,clk,rst;. If(rst= 1) q=0;. Else q=data in;. Posted by 周益賢 at 5:07 下午. 星期五, 3月 17, 2006. Half adder m1(sum,cut,a,b);. And(c,a,b);. 100 b= b;. Module half adder (sum,c out,a,b);. Input a,b;. Output sum,c out;. Wire c out bar;. Xor(sum,a,b);. Nand(c out bar,a,b);. Not(c out,c out bar);. 星期五, 3月 10, 2006.

3

SkyAyu: 吊橋

http://skyayu.blogspot.com/2006/03/blog-post.html

星期五, 3月 31, 2006. Posted by 周益賢 at 5:49 下午. Verilog 硬體描述語言. SynaptiCAD教學網址. SynaptiCAD第一次試跑. SkyAyu歡迎來到我的部落格. 21608;益賢.

4

SkyAyu: Flip_flop

http://skyayu.blogspot.com/2006/05/flipflop.html

星期五, 5月 05, 2006. Reg data in,clk,set,rst;. Flip flop m1(q,data in,clk,set,rst);. 50 data in= data in;. 20 clk= clk;. 30 set= set;. 40 rst= rst;. Module Flip flop(q,data in,clk,set,rst);. Input data in,clk,set,rst;. Always @ (posedge clk). If (rst= 0)q=0;. If (set= 0)q=1;. Posted by 周益賢 at 5:47 下午. Verilog 硬體描述語言. SynaptiCAD教學網址. SynaptiCAD第一次試跑. 21608;益賢.

5

SkyAyu: 比較器

http://skyayu.blogspot.com/2006/05/blog-post.html

星期五, 5月 12, 2006. Reg A0,A1,B0,B1;. Wire A lt B,A gt B,A eq B;. Compare 2 str m1(A lt B,A gt B,A eq B,A0,A1,B0,B1);. 10 A0= A0;. 20 A1= A1;. 30 B0= B1;. 40 B1= B1;. Module compare 2 str(A lt B,A gt B,A eq B,A0,A1,B0,B1);. Input A0,A1,B0,B1;. Output A lt B,A gt B,A eq B;. Wire w1,w2,w3,w4,w5,w6,w7;. Or (A lt B,w1,w2,w3);. Nor (A gt B,A lt B,A eq B);. And (A eq B,w4,w5);. And (w1,w6,B1);. And (w2,w6,w7,B0);. And (w3,w7,B0,B1);. Not (w6,A1);. Not (w7,A0);. Xnor (w4,A1,B1);. Xnor (w5,A0,B0);.

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星期五, 6月 09, 2006. Module test Add rca 4();. Reg [3:0] a,b;. Reg c in;. Wire [3:0] sum;. Wire c out;. Display($time, "c out=%b c in4=%b c in3=%b c in2=%b c in=%b,sum[0]=%b",. C out,M1.c in4,M1.c in3,M1.c in2,c in,sum[0]). 40 c in= c in;. Add rca 4 M1 (sum,c out,a,b,c in);. Module Add rca 4 (sum,c out,a,b,c in);. Output [3:0] sum;. Output c out;. Input [3:0] a,b;. Input c in;. Wire c out,c in4,c in3,c in2;. Add full G1 (sum[0],c in2,a[0],b[0],c in);. Add full G2 (sum[1],c in3,a[1],b[1],c in2);. Input a,b;.

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