asic-world.com
Welcome To Specman Central
http://www.asic-world.com/specman/index.html
In this section you will find tutorial, examples, links, tools and books related to Specman. This section contains a tutorial on e language and Specman. This section contains verification examples using E. List of tools that are used for verification. Some good books on Verification. Some useful links related to Verification. Do you have any Comment?
asic-world.com
Welcome To VHDL Page
http://www.asic-world.com/vhdl/index.html
Welcome To VHDL Page. In this section you will find tutorial, examples, links, tools and books related to VHDL. Add VHDL examples, ported over from Verilog to VHDL. This section contains a practical approach to VHDL. This section contains simple examples using VHDL. List of tools that are used with VHDL. Some good books in VHDL. Some useful links related to VHDL. Do you have any Comment?
asic-world.com
Site FAQ
http://www.asic-world.com/faq.html
You are maitaining a very cool site? Thanks for the feedback, well comments of any kind, help me improve this site. You are welcome to contribute, you can Review the pages, Write some tutorial , tidbits, Suggest new ideas, Pass the link of this website to other people who may find this website useful. I wrote a mail and you never replied why? Why are so many empty sections? When do you expect to complete them? Could you please tell me the answers to question asked in interview? I want to know about you.
asic-world.com
DISCLAIMER
http://www.asic-world.com/disclaimer.html
Do you have any Comment?
scanru.ru
SmartDV ЗАО "СКАН"
http://www.scanru.ru/object.php?id=778
AWR (Applied Wave Research). Москва, ул. Дружбы 10 "Б". Frasl; Все производители. Компания SmartDV является одним из ведущих мировых производителей IP блоков для верификации (VIP). Предлагаемые компанией блоки покрывают большинство существующих стандартных интерфейсов и шин. Тестовое окружение разработано на языках OpenVera, Verilog, SystemC, SystemVerilog и совместимо с такими стандартами верификации как RVM, AVM, VMM, OVM, UVM. СФ-блоки для верификации протоколов MIPI.
asic-world.com
Tidbits
http://www.asic-world.com/tidbits/index.html
This tidbits section was the first one to be written, when I started this website. Over this period of time I have added new topics and corrected mistakes. Also I would like to invite engineers to contribute to this section by reviewing it, writing some tidbits or by suggesting what to add. Wire And Reg In Verilog. Blocking And Nonblocking In Verilog. How to write FSM in Verilog? Interfacing Two Clock Domains. Do you have any Comment?
asic-world.com
Welcome To Scripting Page
http://www.asic-world.com/scripting/index.html
In this section you will find tutorial, examples, links, tools and books related to Scripting, Unix. This section contains a tutorials on writing Makefile, Perl, TCL, shell, Unix Commands. Things that you need to make yourself comfortable in ASIC WORLD. This section contains examples on scripting. List of tools that you may want to install on your machine. Some good books on Scripting. Some useful links related to Scripting. Do you have any Comment?
asic-world.com
Marketing Opportunities
http://www.asic-world.com/sponsor.html
There are mutliple level of sponsorship, you can sponsor whole website, or a section (like complete SystemVerilog Section) or, particular chapter or page in a section. As sponsor, your company names gets mentioned, and you are allowed to place banners in the pages that you have chosen to sponsor. Duration of sponsore can be anything from 3 months to 1 year. Based on your marketing needs, we can customize our pages. Please let us know. Do you have any Comment?
asic-world.com
Brief History
http://www.asic-world.com/history.html
Completed VMM, AOP, System tasks and functional coverage chapters in systemverilog. Completed Specman functional coverage chapter. Completed VERA functional coverage chapter. Completed writing of few pages in RVM, will close this fast. After a long break, started again with website update. Started working on VMM, OVM and RVM. Almost completed the VERA tutorial. Started working on SystemVerilog Section. Start new section on PSL. Will finish this in less then 2 Months. Almost completed the SystemC tutorial.
scanru.com
SmartDV ЗАО "СКАН"
http://www.scanru.com/object.php?id=778
AWR (Applied Wave Research). Москва, ул. Дружбы 10 "Б". Frasl; Все производители. Компания SmartDV является одним из ведущих мировых производителей IP блоков для верификации (VIP). Предлагаемые компанией блоки покрывают большинство существующих стандартных интерфейсов и шин. Тестовое окружение разработано на языках OpenVera, Verilog, SystemC, SystemVerilog и совместимо с такими стандартами верификации как RVM, AVM, VMM, OVM, UVM. СФ-блоки для верификации протоколов MIPI.
SOCIAL ENGAGEMENT