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shengyushen's academic research

CCS'03: Randomized instruction set emulation to disrupt binary code injection attacks. This paper is very similar to the previous one, except that is store the original program on disk, and randomize it while loading it into memory. And its key is very long, may be as long as the program. CCS'03:Countering Code-Injection Attacks With Instruction-Set Randomization. ASPLOS'10:Speculative Parallelization Using Software Multi-threaded Transactions. ASPLOS'10: Inter-Core Cooperative TLB Prefetchers for Chip M...

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CCS'03: Randomized instruction set emulation to disrupt binary code injection attacks. This paper is very similar to the previous one, except that is store the original program on disk, and randomize it while loading it into memory. And its key is very long, may be as long as the program. CCS'03:Countering Code-Injection Attacks With Instruction-Set Randomization. ASPLOS'10:Speculative Parallelization Using Software Multi-threaded Transactions. ASPLOS'10: Inter-Core Cooperative TLB Prefetchers for Chip M...

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shengyushen's academic research | ssypub.blogspot.com Reviews

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CCS'03: Randomized instruction set emulation to disrupt binary code injection attacks. This paper is very similar to the previous one, except that is store the original program on disk, and randomize it while loading it into memory. And its key is very long, may be as long as the program. CCS'03:Countering Code-Injection Attacks With Instruction-Set Randomization. ASPLOS'10:Speculative Parallelization Using Software Multi-threaded Transactions. ASPLOS'10: Inter-Core Cooperative TLB Prefetchers for Chip M...

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shengyushen's academic research: ASPLOS'10:Speculative Parallelization Using Software Multi-threaded Transactions

http://ssypub.blogspot.com/2012/02/asplos10speculative-parallelization.html

ASPLOS'10:Speculative Parallelization Using Software Multi-threaded Transactions. This paper proposes a software transaction memory system that can maintain automic across multiple thread. 订阅：帖子评论 (Atom). CCS03: Randomized instruction set emulation to di. CCS03:Countering Code-Injection Attacks With Inst. ASPLOS10:Speculative Parallelization Using Softwa. ASPLOS10: COMPASS: A Programmable Data Prefetcher. ASPLOS10: Dynamically Replicated Memory: Building. ASPLOS10: Inter-Core Cooperative TLB Prefetchers .

2

shengyushen's academic research: ASPLOS'10:Dynamic Filtering: Multi-Purpose Architecture Support for Language Runtime Systems

http://ssypub.blogspot.com/2012/02/asplos10dynamic-filtering-multi-purpose.html

ASPLOS'10:Dynamic Filtering: Multi-Purpose Architecture Support for Language Runtime Systems. This paper proposes a hardware mechanism and instrutions to detect the rare cases that checked repeatedly in STM and GC for some address patten. 订阅：帖子评论 (Atom). CCS03: Randomized instruction set emulation to di. CCS03:Countering Code-Injection Attacks With Inst. ASPLOS10:Speculative Parallelization Using Softwa. ASPLOS10: COMPASS: A Programmable Data Prefetcher. ASPLOS10: Dynamically Replicated Memory: Building.

3

shengyushen's academic research: ISCA'10: Necromancer: Enhancing System Throughput by Animating Dead Cores

http://ssypub.blogspot.com/2012/02/isca10-necromancer-enhancing-system.html

ISCA'10: Necromancer: Enhancing System Throughput by Animating Dead Cores. In manufactoring test, any core that can not pass will be disabled, but they are most correct with only minor bugs. So this paper use them to run ahead and direct a simpler core with useful information, such as branch destination and cache prefetch, thus lead to bettern performance on the simpler core. 订阅：帖子评论 (Atom). CCS03: Randomized instruction set emulation to di. CCS03:Countering Code-Injection Attacks With Inst.

4

shengyushen's academic research: 十一月 2011

http://ssypub.blogspot.com/2011_11_01_archive.html

MICRO'11: Architectural Support for Secure Virtualization under a Vulnerable Hypervisor. To prevent the hypervisor from reading the guest VM's memory, this paper proposes hardware mechanism to hide the VM's status and memory owner mapping table from the hypervisor. The hypervisor can still access these VM's private information be calling this novel hardware. MICRO'11: Towards the Ideal On-chip Fabric for 1-to-Many and Many-to-1 Communication. So when produced with a kripke structure M with recurence diam...

5

shengyushen's academic research: ISCA'10 : ynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance

http://ssypub.blogspot.com/2012/02/isca10-ynamic-warp-subdivision-for.html

ISCA'10 : ynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance. This paper proposes to divide the SIMD lanes into two seperate sets on lane Divergence caused by different in branch or memory latency. And then these sets can be executed as threads interleaved. 订阅：帖子评论 (Atom). CCS03: Randomized instruction set emulation to di. CCS03:Countering Code-Injection Attacks With Inst. ASPLOS10:Speculative Parallelization Using Softwa. ASPLOS10: COMPASS: A Programmable Data Prefetcher.

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shengyushen's academic research

CCS'03: Randomized instruction set emulation to disrupt binary code injection attacks. This paper is very similar to the previous one, except that is store the original program on disk, and randomize it while loading it into memory. And its key is very long, may be as long as the program. CCS'03:Countering Code-Injection Attacks With Instruction-Set Randomization. ASPLOS'10:Speculative Parallelization Using Software Multi-threaded Transactions. ASPLOS'10: Inter-Core Cooperative TLB Prefetchers for Chip M...

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