thecodecavern.co.uk thecodecavern.co.uk

thecodecavern.co.uk

The Code Cavern

To the Code Cavern , an underground repository of highly optimized. Mining for optimal sequences). Fully take advantage of the cpu's we typically have to write different. Versions for each micro-architecture , we consider those below as x64. There are a number of subdivisions mainly todo with L1 Data cache access , I consider the latest one. Like the latest K8 but SSE is faster and a few new instructions. 45nm , appears to be a tweeked K10 with improved load-store. Fusion of K8 and GPU. 26 30 31 46.

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The Code Cavern | thecodecavern.co.uk Reviews
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To the Code Cavern , an underground repository of highly optimized. Mining for optimal sequences). Fully take advantage of the cpu's we typically have to write different. Versions for each micro-architecture , we consider those below as x64. There are a number of subdivisions mainly todo with L1 Data cache access , I consider the latest one. Like the latest K8 but SSE is faster and a few new instructions. 45nm , appears to be a tweeked K10 with improved load-store. Fusion of K8 and GPU. 26 30 31 46.
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1 the code cavern
2 welcome
3 assembler code
4 micro architecture
5 family
6 model
7 bobcat
8 bulldozer
9 penryn
10 nehalem
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the code cavern,welcome,assembler code,micro architecture,family,model,bobcat,bulldozer,penryn,nehalem,westmere,sandybridge,32nm with avx,atom,only one model,nano,agner fogs software,optimization resources,data format,name,binary digit array,gmp's mpn
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The Code Cavern | thecodecavern.co.uk Reviews

https://thecodecavern.co.uk

To the Code Cavern , an underground repository of highly optimized. Mining for optimal sequences). Fully take advantage of the cpu's we typically have to write different. Versions for each micro-architecture , we consider those below as x64. There are a number of subdivisions mainly todo with L1 Data cache access , I consider the latest one. Like the latest K8 but SSE is faster and a few new instructions. 45nm , appears to be a tweeked K10 with improved load-store. Fusion of K8 and GPU. 26 30 31 46.

INTERNAL PAGES

thecodecavern.co.uk thecodecavern.co.uk
1

AMD copy

http://www.thecodecavern.co.uk/k8/copy.html

All the AMD chips are limited by the ld/st bandwidth of 2 mem ops per cycle , so the best we can achieve is 1.0c/w for non-sse and 0.75 for SSE on the K10/K10-2. A 4-way unroll achieves the optimal non-SSE speed in both incrementing and decrementing versions. A 2-way unroll may work but as with store on the K8 we expect problems reaching the optimal speed. The wind-down code could be cleaned up somewhat. The SSE version for the K10 needs to be writen.

2

K10 popham

http://www.thecodecavern.co.uk/k8/k10/popham.html

The K10 has the new popcnt instruction which is in the single ABM execution unit , therefore we should be able to get 1.0c/w , however for hamdist we are also limited by the retirement of macro-ops to 1.333 € c/w. For popcount macro-op retirement and 2c per loop says that a 2-way unroll is the minimum , pick hardware implies pipelining is needed and we can get the optimal 1.0c/w popcount. For hamdist a 4-way unroll gives us 1.5c/w hamdist.

3

Nehalem popham

http://www.thecodecavern.co.uk/nehalem/popham.html

The nehalem/westmere has the new popcnt instruction which has a thruput of 1 per cycle , therefore we should be able to get 1.0c/w for popcount and 2.0c/w for hamdist bound by ld/st. Which runs at 1.0c/w. Which runs at 2.0c/w. Using a mixed int/SSE it should be possible to break the ld/st bound in hamdist and improve on the times of 2.0c/w.

4

store

http://www.thecodecavern.co.uk/core2/shift.html

We can use the double shift instructions SHLD/SHRD on the intel chips , these take 2 micro-ops giving us an optimal sequence of load,shld,store consisting of 4 micro-ops which takes 1c in the RAT , so we expect 1.0 € c/w : NOTE as jump/loop are only processed in pipe 5 (unlike AMD) we must have a whole number of cycles in the intel loops. Takes 1.25 c/w. Takes 1.25 c/w. The wind-down code could be cleaned up somewhat. So we need to unroll it some more?

5

AMD shift

http://www.thecodecavern.co.uk/k8/shift.html

For the amount of unrolling all these functions are optimal (bounded by macro-op retirement). K8 takes 2.0 € c/w. K10 takes 1.333 € c/w. K10 lshift decr takes 1.5 € c/w. K8 lshift decr 4way. Runs at 2.166 c/w. K8 rshift incr 4way. Runs at 2.166 c/w. K10 lshift decr 4way. Runs at 1.666 c/w. K10 lshift incr 4way. Runs at 1.5 c/w DO THIS? K10 rshift incr 4way. Runs at 1.5 c/w. The wind-down code could be cleaned up somewhat. For the K8 and K10. Lshift by 1 inplace. Runs at 1.0 c/w. Rshift by 1 inplace.

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To the Code Cavern , an underground repository of highly optimized. Mining for optimal sequences). Fully take advantage of the cpu's we typically have to write different. Versions for each micro-architecture , we consider those below as x64. There are a number of subdivisions mainly todo with L1 Data cache access , I consider the latest one. Like the latest K8 but SSE is faster and a few new instructions. 45nm , appears to be a tweeked K10 with improved load-store. Fusion of K8 and GPU. 26 30 31 46.

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