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Design For TestA blog about DFT( Design for Test)
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A blog about DFT( Design for Test)
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A blog about DFT( Design for Test)
vlsi-doubts.blogspot.com
Design For Test: DFT Q&A - Part 26
http://vlsi-doubts.blogspot.com/2013/09/dft-q-part-26.html
Wednesday, September 11, 2013. DFT Q&A - Part 26. What all things in DFT can be of a concern whenever there is a technology node change? There are many changes in DFT with the nodes. In fact DFT is expanding as the technology is shrinking. Some of the things to take care of are :. 3 Programmability : The biggest ask for DFT today is programmability, be it IOs, logic or memory tests. Can I get some information regarding the IO BIST? Since capturing data from such high speed I/Os is not possible for low co...
Design For Test: DFT Q & A- part 1
http://vlsi-doubts.blogspot.com/2013/09/dft-q-part-1.html
Wednesday, September 11, 2013. DFT Q and A- part 1. 1 What is sequential Depth In DFT? How does it improve coverage? Ans: FastScan performs clock sequential test generation if you specify a non-zero sequential depth. Clock sequential identification selects scannable cells by cutting sequential loops and limiting sequential depth based on the -Depth switch. Typically, this method is used to create structured partial scan designs that can use the FastScan clock sequential ATPG algorithm. Ans: Difference be...
Design For Test: DFT Q & A - Part 2
http://vlsi-doubts.blogspot.com/2013/09/dft-q-part3.html
Wednesday, September 11, 2013. DFT Q and A - Part 2. 6 If we provide controllability and observability to the ports of area under test, will it improve the test coverage? If yes, how much %age of improvement can we see? Ans: yes, we can see an improvement in coverage. Think about the bounding logic that we usually give for macros. The improvement in coverage will depend on the initial coverage without bound and the no of faults in the design under test. Let us assume that in a path there are some 10 node...
Design For Test: March 2010
http://vlsi-doubts.blogspot.com/2010_03_01_archive.html
Wednesday, March 17, 2010. C-to-Verilog is a free service for circuit designers.Visitors can create hardware circuits using the service provided here on this website. Users may submit their C programs and download a verilog module which can then be embedded on FPGAs.Website will automatically synthesize the C program into a verilog module. For additional information on how to use our website, watch the screencast. Http:/ www.c-to-verilog.com/index.html. Wednesday, March 17, 2010. Links to this post.
Design For Test: Combinational Loops
http://vlsi-doubts.blogspot.com/2013/12/combinational-loops.html
Monday, December 16, 2013. You would often hear backend engineers remonstrating the frontend design folks on the presence of combinational loops in the design. But why do they create such a hue and cry? What possibly could one or maybe few combinational loops do? Well, potentially, they can render the entire functionality of the SoC haywire and not taken care off. And some combinational loops, on the other hand, are indispensable for the evolution of a particular technology. We'll see how and why. Well, ...
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VLSI ASIC & FPGA
VLSI ASIC and FPGA. Wednesday, February 13, 2008. CDC - Clock Domain Crossing guidelines. A good article on CDC guidelines. Understanding Clock Domain Crossing Issues. Asynchronous signals in a synchronous world. Links to this post. Tuesday, January 29, 2008. Flip Flops and Register timings. The two important timings of a flip flop are. Links to this post. Divide by 3.5 clock divider. Divide by 3.5 clock divider. Divide by 3 first and add the negedge flop in series to make divide by 3.5. Divide by 3 = =.
VLSI Basics And Interview Questions
VLSI Basics And Interview Questions. This Blog is created for Basic VLSI Interview Questions. This content is purely VLSI Basics. Sub Child Category 1. Sub Child Category 2. Sub Child Category 3. Wednesday, 30 April 2014. Here I am going to discuss about Tie Cells Insertion. Before going to know about Tie Cells Insertion, We have to know what Tie Cells are. Tie High Cell is special purpose standard cell whose output is Constant High (Vdd). Why Tie cells are inserted? In lower technology nodes the gate ox...
ASIC/VLSI Basic Concept
ASCI/VLSI Basic Concept blog try to collect basic concept for ASIC IC Designs, including front-end and back-end. Wednesday, September 7, 2011. VCD File In Power Analysis. VCD Stands for Value Change Dump, VCD file is used for verilog simulation and power analysis. VCD file is an ASCII format file include waveform information, this file is used by Verilog simulators. VCD file fromat is defined by IEEE Standard 1364. Tuesday, July 5, 2011. ICC procedure: dump layout window snapshot. Get placement utilizati...
VLSI Concepts - Home
VLSI Concepts was founded in 1995 by Dr. Edward L. Hepler. Dr Hepler began his career as a Member of Technical Staff in the Processor Design laboratory of Bell Laboratories where he helped design high reliability processors used in electronic switching systems. From there he moved to the Space Systems Division of General Electric and then to Commodore Business Machines where he developed chips for next generation Amiga machines. . VLSI Concepts - Cores. VLSI Concepts - Consulting.
VLSI Core - IC Design Technology Experts
Design For Test
Tuesday, December 24, 2013. Clock Jargon: Important Terms. Clock to an SoC is like blood to a human body. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the SoC. There are many terms which modern designers use in relation to the clock and while building the Clock Tree, the backend team carefully monitors these. Let's have a look at them. Consider a hierarchical design where we have...
VLSI-EDA Laboratory
vlsi-encyclopedia.blogspot.com
VLSI Encyclopedia
ENHANCE YOUR KNOWLEDGE OF VLSI DOMAIN. HERE YOU CAN FIND THE TOPICS REGARDING VLSI DESIGNING AND VERIFICATION SUCH AS DIGITAL DESIGNING BASICS, TIMING ANALYSIS, SYNTHESIS AND SIMULATION, VHDL, VERILOG, SYSTEM VERILOG, ASICS AND MUCH MORE. SO COME AND EXPLORE YOUR KNOWLEDGE OF VLSI. Saturday, July 28, 2012. Very Large Scale Integration (VLSI): VLSID 2013 - 26th International Conference on VLSI. Very Large Scale Integration (VLSI): VLSID 2013 - 26th International Conference on VLSI. Friday, January 6, 2012.
VLSI Concepts
You will find the basics of VLSI design in this place. Monday, August 3, 2015. Dishing and Erosion (CMP). CMP (Chemical Mechanical Planarization) (Part 3). Till now we have discussed about the CMP process, Importance of CMP and problem raised by side effects (Dishing and Erosion) of CMP. But still we didn’t discuss the reason of Dishing and Erosion (what’s the root cause of these), definition of these Manufacturing defects. And how can we minimize these. In this article, let’s focus on these points.
nikhil saxena
VLSI FAQS
LOOKING FOR XILINX FPGA BOARDS. Verilog Course Team is now authorized distributor for Digilent-Xilinx FPGA Boards, For more details visit www.verilogcourseteam.com/products. Or Contact @ 91 9894220795. Wednesday, July 23, 2008. Verilog Coding Guidelines- Part 5. 51 One file, one module. Create separate files for each modules. Name the file. V The only exceptions for this. File naming convention shall be the technology-dependent modules (top module or macro. Include relevant part of the spec. Listing the ...
