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Analog and Mixed Signal VLSI at WPI

Analog and Mixed Signal VLSI at WPI. About Analog and Mixed Signal VLSI. Split ADC" Background Linearization of VCO-Based ADCS. Design of a Sub-Picosecond-Jitter Delay-Lock-Loop for Interleaved ADC Sample Clock Synthesis. Digital Background Calibration of Redundant Split-Flash ADC in 180nm CMOS. An 8-b 1GS/s FLASH ADC in 45nm CMOS. A Real Time Autonomous and Intelligent RF System. Self-Calibration of a High Resolution Interleaved ADC using the "Split ADC" Architecture. Jitter in CMOS Ring Oscillators.

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Analog and Mixed Signal VLSI at WPI | vlsi.wpi.edu Reviews

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Analog and Mixed Signal VLSI at WPI. About Analog and Mixed Signal VLSI. Split ADC Background Linearization of VCO-Based ADCS. Design of a Sub-Picosecond-Jitter Delay-Lock-Loop for Interleaved ADC Sample Clock Synthesis. Digital Background Calibration of Redundant Split-Flash ADC in 180nm CMOS. An 8-b 1GS/s FLASH ADC in 45nm CMOS. A Real Time Autonomous and Intelligent RF System. Self-Calibration of a High Resolution Interleaved ADC using the Split ADC Architecture. Jitter in CMOS Ring Oscillators.

<META> KEYWORDS

1 contact information

2 microelectronics i

3 microelectronics ii

4 cadence tutorial

5 publications

6 list of publications

7 wpi homepage

8 department homepage

9 credits

10 access statistics

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Analog and Mixed Signal VLSI at WPI | vlsi.wpi.edu Reviews

https://vlsi.wpi.edu

Analog and Mixed Signal VLSI at WPI. About Analog and Mixed Signal VLSI. Split ADC" Background Linearization of VCO-Based ADCS. Design of a Sub-Picosecond-Jitter Delay-Lock-Loop for Interleaved ADC Sample Clock Synthesis. Digital Background Calibration of Redundant Split-Flash ADC in 180nm CMOS. An 8-b 1GS/s FLASH ADC in 45nm CMOS. A Real Time Autonomous and Intelligent RF System. Self-Calibration of a High Resolution Interleaved ADC using the "Split ADC" Architecture. Jitter in CMOS Ring Oscillators.

INTERNAL PAGES

vlsi.wpi.edu

1

Jitter in CMOS Ring Oscillators

http://www.vlsi.wpi.edu/jitter/index.html

Extension of Bipolar Ring Jitter Theory to CMOS. Interpolating ring VCO composed of differential pair gates (CMOS analogs of the 155MHz and 622MHz rings). A Current Controlled Oscillator (CCO) with single-ended inverter gates. For each of the above, rings of different lengths (to test whether the design figure-of-merit in [1, 2] is also independent of ring length in CMOS). Clock-division circuitry to allow the basic ring architecture to span the required frequency range for the applications of interest.

2

List of Publications

http://www.vlsi.wpi.edu/publications/index.html

J McNeill, M. Coln, B. Larivee, "A Split-ADC Architecture for a Deterministic Digital. Background Calibration of a 16b 1MS/s ADC," ISSCC Dig. Tech. Papers, pp. 277-278, Feb. 2005. Publications Prior to 2000. These pages by Chris David.

3

ISCAS98: A compact 31-input programmable majority gate based on CapacitiveThreshold Logic

http://www.vlsi.wpi.edu/FPGA_Manual/index.html

Guide to Synthesis and Implementation Tools for VHDL Modeling and Design.

4

Cadence University Program Member

http://www.vlsi.wpi.edu/cadence/index.html

The Analog IC Laboratory at WPI has been established in May 1998 as a state-of-the-art research and education facility for digital and mixed-signal integrated circuit design. The aim of the laboratory is to provide a comprehensive design environment for the development of novel integrated circuit and VLSI architectures, and to facilitate hands-on education of undergraduate and graduate students in all aspects of IC design. Various submicron fabrication technologies. A Tutorial for CADENCE Design Suite.

5

About Analog and Mixed Signal VLSI at WPI

http://www.vlsi.wpi.edu/about/index.html

About Analog and Mixed Signal VLSI at WPI. Cadence Design Tools at WPI. New England Center for Analog and Digital IC Design. Cadence Design Tools at WPI. New England Center for Analog and Digital IC Design. These pages by Chris David.

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Analog and Mixed Signal VLSI at WPI

Analog and Mixed Signal VLSI at WPI. About Analog and Mixed Signal VLSI. Split ADC" Background Linearization of VCO-Based ADCS. Design of a Sub-Picosecond-Jitter Delay-Lock-Loop for Interleaved ADC Sample Clock Synthesis. Digital Background Calibration of Redundant Split-Flash ADC in 180nm CMOS. An 8-b 1GS/s FLASH ADC in 45nm CMOS. A Real Time Autonomous and Intelligent RF System. Self-Calibration of a High Resolution Interleaved ADC using the "Split ADC" Architecture. Jitter in CMOS Ring Oscillators.

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