voicexixi.blogspot.com

White Flag

Http:/ whiteflag.wikidot.com. Thursday, August 11, 2011. Reset bridge circuit asserts asynchronously and deasserts synchronously. Wednesday, August 10, 2011. A white paper from Mentor. Click following link to read the paper. It's in my dropbox. Signal Integrity from Mentor. Tuesday, June 28, 2011. Define HDL Macro via quartus command line. Quartus map my design - verilog macro="a=2". An example in Makefile:. MAP ARGS = - verilog macro="a=$(A ID)". QUARTUS MAP BIN) $(MAP ARGS) $(PROJECT) -c $(REVISION).

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Http:/ whiteflag.wikidot.com. Thursday, August 11, 2011. Reset bridge circuit asserts asynchronously and deasserts synchronously. Wednesday, August 10, 2011. A white paper from Mentor. Click following link to read the paper. It's in my dropbox. Signal Integrity from Mentor. Tuesday, June 28, 2011. Define HDL Macro via quartus command line. Quartus map my design - verilog macro=a=2. An example in Makefile:. MAP ARGS = - verilog macro=a=$(A ID). QUARTUS MAP BIN) $(MAP ARGS) $(PROJECT) -c $(REVISION).

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White Flag | voicexixi.blogspot.com Reviews

https://voicexixi.blogspot.com

Http:/ whiteflag.wikidot.com. Thursday, August 11, 2011. Reset bridge circuit asserts asynchronously and deasserts synchronously. Wednesday, August 10, 2011. A white paper from Mentor. Click following link to read the paper. It's in my dropbox. Signal Integrity from Mentor. Tuesday, June 28, 2011. Define HDL Macro via quartus command line. Quartus map my design - verilog macro="a=2". An example in Makefile:. MAP ARGS = - verilog macro="a=$(A ID)". QUARTUS MAP BIN) $(MAP ARGS) $(PROJECT) -c $(REVISION).

INTERNAL PAGES

voicexixi.blogspot.com

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White Flag: July 2010

http://www.voicexixi.blogspot.com/2010_07_01_archive.html

Http:/ whiteflag.wikidot.com. Thursday, July 29, 2010. How to: CVS merge from trunk to branch. Cvs up -d -j HEAD. How to: CVS import without any ignore files. Thursday, July 15, 2010. How to generate Modelsim libs of Xilinx. 2 In design Utilites , choose Compile HDL Simulation Libraries. 3 Right click, goto Process Properties. 4 Set Simulator path properly, Choose Language to ALL/Verilog/VHDL. 5 Run the utility. XILINX LIB PATH is the path for output. Note: glbl.v from Xilinx is also needed.

2

White Flag: August 2009

http://www.voicexixi.blogspot.com/2009_08_01_archive.html

Http:/ whiteflag.wikidot.com. Friday, August 28, 2009. Http:/ owen.sj.ca.us/ rk/howto/cvs.html#tag. Http:/ www.network-theory.co.uk/docs/cvsmanual/. Subscribe to: Posts (Atom). View my complete profile.

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White Flag: May 2011

http://www.voicexixi.blogspot.com/2011_05_01_archive.html

Http:/ whiteflag.wikidot.com. Friday, May 13, 2011. Improve performance by adding pipeline and also adopting packet layer for MM interface. Q: what about the latency of MM command? A Qsys can be re-used as a sub-system. The conduit interface can be either connected within a Qsys or export to top, which is very good. V doesn't include the source files anymore. will need to adjust script to get rtl file list. Qsys doesn't generate cpu.v which includes rtl source files and path. Monday, May 9, 2011. Note: I...

4

White Flag: June 2011

http://www.voicexixi.blogspot.com/2011_06_01_archive.html

Http:/ whiteflag.wikidot.com. Tuesday, June 28, 2011. Define HDL Macro via quartus command line. Quartus map my design - verilog macro="a=2". An example in Makefile:. MAP ARGS = - verilog macro="a=$(A ID)". QUARTUS MAP BIN) $(MAP ARGS) $(PROJECT) -c $(REVISION). Note: If the macro has been already defined in HDL, the definition here in command line won't override it. So, make sure remove the definition in HDL. To make simulation happy,. Set global assignment -name VERILOG MACRO "a=2".

5

White Flag: January 2011

http://www.voicexixi.blogspot.com/2011_01_01_archive.html

Http:/ whiteflag.wikidot.com. Wednesday, January 26, 2011. Handle rectangle in Emacs. Commands operate on rectangular areas of the text: all the characters between a certain pair of columns, in a certain range of lines. Emacs has commands to kill rectangles, yank killed rectangles, clear them out, fill them with blanks or text, or delete them. Rectangle commands are useful with text in multicolumn formats, and for changing text into or out of such formats. Delete the text of the region-rectangle (. Clear...

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White Flag

Http:/ whiteflag.wikidot.com. Thursday, August 11, 2011. Reset bridge circuit asserts asynchronously and deasserts synchronously. Wednesday, August 10, 2011. A white paper from Mentor. Click following link to read the paper. It's in my dropbox. Signal Integrity from Mentor. Tuesday, June 28, 2011. Define HDL Macro via quartus command line. Quartus map my design - verilog macro="a=2". An example in Makefile:. MAP ARGS = - verilog macro="a=$(A ID)". QUARTUS MAP BIN) $(MAP ARGS) $(PROJECT) -c $(REVISION).

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