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On My Way to Permanent Head Damage. Sunday, 26 January 2014. Brief history of (Altera's) FPGA. Ron Wilson at Altera did a very nice three-part write-up which I dub as Brief history of (Altera's) FPGA. In the Beginning,. Http:/ www.altera.com/technology/system-design/articles/2013/in-the-beginning.html. From Glue Logic to Subsystem: Altera's Second Decade - See more at: http:/ www.altera.com/technology/system-design/articles/2013/glue-logic-subsystem.html#sthash.T6a0DZh9.dpuf. Thursday, 23 January 2014.

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On My Way to Permanent Head Damage. Sunday, 26 January 2014. Brief history of (Altera's) FPGA. Ron Wilson at Altera did a very nice three-part write-up which I dub as Brief history of (Altera's) FPGA. In the Beginning,. Http:/ www.altera.com/technology/system-design/articles/2013/in-the-beginning.html. From Glue Logic to Subsystem: Altera's Second Decade - See more at: http:/ www.altera.com/technology/system-design/articles/2013/glue-logic-subsystem.html#sthash.T6a0DZh9.dpuf. Thursday, 23 January 2014.

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XIAOLEIC | xiaoleicestustc.blogspot.com Reviews

https://xiaoleicestustc.blogspot.com

On My Way to Permanent Head Damage. Sunday, 26 January 2014. Brief history of (Altera's) FPGA. Ron Wilson at Altera did a very nice three-part write-up which I dub as Brief history of (Altera's) FPGA. In the Beginning,. Http:/ www.altera.com/technology/system-design/articles/2013/in-the-beginning.html. From Glue Logic to Subsystem: Altera's Second Decade - See more at: http:/ www.altera.com/technology/system-design/articles/2013/glue-logic-subsystem.html#sthash.T6a0DZh9.dpuf. Thursday, 23 January 2014.

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XIAOLEIC: January 2013

http://xiaoleicestustc.blogspot.com/2013_01_01_archive.html

On My Way to Permanent Head Damage. Thursday, 17 January 2013. Converting Verilog code to VHDL. Recently I was working on a hardware project which has a mix of VHDL/ Verilog RTL codes. When I was trying compiling the codes, the compiler reported some errors. After some Google searches as well as discussion with colleagues, I found the reason: some Verilog modules are instantiated in VHDL architectures, and a VHDL-style component declaration is missing for these Verilog modules. Great! Verilog2vhdl -in si...

2

XIAOLEIC: October 2012

http://xiaoleicestustc.blogspot.com/2012_10_01_archive.html

On My Way to Permanent Head Damage. Friday, 26 October 2012. Using Jenkins for hardware project. Reference 1 makes a very good case on why we should employ the concept and practices of continuous integration for hardware design project. I am working on a hardware project, doing Vhdl programming. Like C programming or any software project, I have to make sure that my checkin won't break the design. To ensure this, two basic checks are that the design should be able to compile and elaborate. Will update al...

3

XIAOLEIC: March 2013

http://xiaoleicestustc.blogspot.com/2013_03_01_archive.html

On My Way to Permanent Head Damage. Sunday, 31 March 2013. Whats new in Altera Stratix V. Altera has made it a ritual to publish at ACM FPGA symposium about their Stratix architecture in amazing technical details. And this year, they published about Stratix V. David Lewis et al, Architectural enhancements in Stratix V™, http:/ wiki.tcfpga.org/FPGA2013? Friday, 22 March 2013. Copy all files/ folders from source to destination directory. Use “-r” option. Example:. Check ws status ch.sh*. No error if existi...

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XIAOLEIC: April 2013

http://xiaoleicestustc.blogspot.com/2013_04_01_archive.html

On My Way to Permanent Head Damage. Tuesday, 23 April 2013. Quickly check SDC constraints in Synplify. So I asked Google if there is a way to quickly check SDC file for incorrect constraints. And I saw this article:. Http:/ www.eetimes.com/design/programmable-logic/4402390/Bugs-Be-Gone-? The author recommends that we do constraint check. Synplify Pro/Premier GUI: Run - Constraint check. Or using TCL: project -run constraint check. This will generate a report named * cck.rpt. Tuesday, 9 April 2013. Cm3 tm...

5

XIAOLEIC: February 2013

http://xiaoleicestustc.blogspot.com/2013_02_01_archive.html

On My Way to Permanent Head Damage. Thursday, 28 February 2013. Dual-port RAM invisible from Quartus In-System Memory Content Editor. Today I just found what is said in the title. This is a limitation of using dual-port memory in Altera FPGAs. Basically, if we use dual-port memory, we cannot make this memory run-time modifiable (hence the memory being invisible from In-System Memory Content Editor). Http:/ www.alteraforum.com/forum/showthread.php? Functionality of your design. Wednesday, 27 February 2013.

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XIAOLEIC

On My Way to Permanent Head Damage. Sunday, 26 January 2014. Brief history of (Altera's) FPGA. Ron Wilson at Altera did a very nice three-part write-up which I dub as Brief history of (Altera's) FPGA. In the Beginning,. Http:/ www.altera.com/technology/system-design/articles/2013/in-the-beginning.html. From Glue Logic to Subsystem: Altera's Second Decade - See more at: http:/ www.altera.com/technology/system-design/articles/2013/glue-logic-subsystem.html#sthash.T6a0DZh9.dpuf. Thursday, 23 January 2014.

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