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F9203843: 十月 2006
http://kingerzack.blogspot.com/2006_10_01_archive.html
星期二, 10月 24, 2006. Wire a,b;. System clock #100 clock1(a);. System clock #50 clock2(b);. Module system clock(clk);. Begin#(PERIOD/2) clk= clk;. PERIOD-PERIOD/2) clk= clk;. Endalways @ (posedge clk). Posted by f9203843 @ 2:44 下午. 星期二, 10月 17, 2006. Posted by f9203843 @ 10:02 下午. 星期二, 10月 03, 2006. Posted by f9203843 @ 8:43 下午. Posted by f9203843 @ 1:32 上午. 星期一, 10月 02, 2006. Posted by f9203843 @ 4:32 下午. 21729;林鎮, 大葉大學, Taiwan. 31532;三階段. 31532;二階段. 26032;學期. 31532;三階段考試.
f9203843.blogspot.com
憭批蔬敶剔��摰�
http://f9203843.blogspot.com/2006/09/blog-post.html
Notify Blogger about objectionable content. What does this mean? 撟喳 憭批飛 撠蝢憌敺頞= =. 鈭, 銋 29, 2006. Posted by f9203843 @ 12:12 銝. 銝, 銋 27, 2006. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Wire d,e,f;. Xor(d,a,b);. 頛舫摰,頛詨箇榛,頛詨亦榮,b. And(e,a,b);. 頛舫摰,頛詨箇榷,頛詨亦榮,b. Xor(Sum,d,Cin);. 頛舫摰,頛詨箇搴um,頛詨亦榛,Cin. And(f,d,Cin);. 頛舫摰,頛詨箇榻,頛詨亦榛,Cin. Or(Cout,f,e);. 頛舫摰,頛詨箇慢out,頛詨亦榻,e. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Assign {Cout,Sum}=a b Cin;. Input a,b,Cin;.
f9203843.blogspot.com
憭批蔬敶剔��摰�
http://f9203843.blogspot.com/2006/09/blog-post_115934459942445455.html
Notify Blogger about objectionable content. What does this mean? 撟喳 憭批飛 撠蝢憌敺頞= =. 鈭, 銋 29, 2006. Posted by f9203843 @ 12:12 銝. 銝, 銋 27, 2006. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Wire d,e,f;. Xor(d,a,b);. 頛舫摰,頛詨箇榛,頛詨亦榮,b. And(e,a,b);. 頛舫摰,頛詨箇榷,頛詨亦榮,b. Xor(Sum,d,Cin);. 頛舫摰,頛詨箇搴um,頛詨亦榛,Cin. And(f,d,Cin);. 頛舫摰,頛詨箇榻,頛詨亦榛,Cin. Or(Cout,f,e);. 頛舫摰,頛詨箇慢out,頛詨亦榻,e. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Assign {Cout,Sum}=a b Cin;. Input a,b,Cin;.
f9203843.blogspot.com
憭批蔬敶剔��摰�
http://f9203843.blogspot.com/2006/09/blog-post_26.html
Notify Blogger about objectionable content. What does this mean? 撟喳 憭批飛 撠蝢憌敺頞= =. 鈭, 銋 29, 2006. Posted by f9203843 @ 12:12 銝. 銝, 銋 27, 2006. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Wire d,e,f;. Xor(d,a,b);. 頛舫摰,頛詨箇榛,頛詨亦榮,b. And(e,a,b);. 頛舫摰,頛詨箇榷,頛詨亦榮,b. Xor(Sum,d,Cin);. 頛舫摰,頛詨箇搴um,頛詨亦榛,Cin. And(f,d,Cin);. 頛舫摰,頛詨箇榻,頛詨亦榛,Cin. Or(Cout,f,e);. 頛舫摰,頛詨箇慢out,頛詨亦榻,e. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Assign {Cout,Sum}=a b Cin;. Input a,b,Cin;.
f9203843.blogspot.com
憭批蔬敶剔��摰�
http://f9203843.blogspot.com/2006/09/blog-post_29.html
Notify Blogger about objectionable content. What does this mean? 撟喳 憭批飛 撠蝢憌敺頞= =. 鈭, 銋 29, 2006. Posted by f9203843 @ 12:12 銝. 銝, 銋 27, 2006. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Wire d,e,f;. Xor(d,a,b);. 頛舫摰,頛詨箇榛,頛詨亦榮,b. And(e,a,b);. 頛舫摰,頛詨箇榷,頛詨亦榮,b. Xor(Sum,d,Cin);. 頛舫摰,頛詨箇搴um,頛詨亦榛,Cin. And(f,d,Cin);. 頛舫摰,頛詨箇榻,頛詨亦榛,Cin. Or(Cout,f,e);. 頛舫摰,頛詨箇慢out,頛詨亦榻,e. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Assign {Cout,Sum}=a b Cin;. Input a,b,Cin;.
kingerzack.blogspot.com
F9203843: 四月 2007
http://kingerzack.blogspot.com/2007_04_01_archive.html
星期一, 4月 30, 2007. Posted by f9203843 @ 11:46 下午. 星期一, 4月 09, 2007. Define NUM STATE BITS 2. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Begin @(posedge sysclk) enter new state(`IDLE);. Posedge sysclk) enter new state(`COMPUTE123);. Posedge sysclk) enter new state(`COMPUTE1234);.
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F9203843: 五月 2007
http://kingerzack.blogspot.com/2007_05_01_archive.html
星期一, 5月 07, 2007. Posted by f9203843 @ 8:50 下午. 21729;林鎮, 大葉大學, Taiwan. 31532;三階段. 31532;二階段. 20170;日第一階段考試結果9X9. 20170;日混合式除法機模擬圖和執行畫面. 31532;一階段 乘法機完成. 3月12日 紅綠燈挑戰. 26032;學期. 31532;四階段自我測驗Part-2. 31532;四階段自我測驗. 31532;三階段考試.
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F9203843: 九月 2006
http://kingerzack.blogspot.com/2006_09_01_archive.html
星期五, 9月 29, 2006. Posted by f9203843 @ 12:12 上午. 星期三, 9月 27, 2006. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Wire d,e,f;. Xor(d,a,b);. 邏輯閘宣告,輸出為d,輸入為a,b. And(e,a,b);. 邏輯閘宣告,輸出為e,輸入為a,b. Xor(Sum,d,Cin);. 邏輯閘宣告,輸出為Sum,輸入為d,Cin. And(f,d,Cin);. 邏輯閘宣告,輸出為f,輸入為d,Cin. Or(Cout,f,e);. 邏輯閘宣告,輸出為Cout,輸入為f,e. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Assign {Cout,Sum}=a b Cin;. Module fulladder(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Posted ...
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F9203843: 十二月 2006
http://kingerzack.blogspot.com/2006_12_01_archive.html
星期二, 12月 26, 2006. Posted by f9203843 @ 8:43 下午. 21729;林鎮, 大葉大學, Taiwan. 31532;三階段. 31532;二階段. 20170;日第一階段考試結果9X9. 20170;日混合式除法機模擬圖和執行畫面. 31532;一階段 乘法機完成. 3月12日 紅綠燈挑戰. 26032;學期. 31532;四階段自我測驗Part-2. 31532;四階段自我測驗. 31532;三階段考試.