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F9203843

星期一, 5月 07, 2007. Posted by f9203843 @ 8:50 下午. 星期一, 4月 30, 2007. Posted by f9203843 @ 11:46 下午. 星期一, 4月 09, 2007. Define NUM STATE BITS 2. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Begin @(posedge sysclk) enter new state(`IDLE);. Posedge sysclk) enter new state(`COMPUTE123);. Reg clk,reset;.

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F9203843 | kingerzack.blogspot.com Reviews

<META> DESCRIPTION

星期一, 5月 07, 2007. Posted by f9203843 @ 8:50 下午. 星期一, 4月 30, 2007. Posted by f9203843 @ 11:46 下午. 星期一, 4月 09, 2007. Define NUM STATE BITS 2. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Begin @(posedge sysclk) enter new state(`IDLE);. Posedge sysclk) enter new state(`COMPUTE123);. Reg clk,reset;.

<META> KEYWORDS

1 平凡無奇的大學生

2 第三階段

3 0 comments

4 第二階段

5 今日第一階段考試結果9x9

6 模擬結果圖

7 模擬程式碼

8 define idle 2'b00

9 module cl clk ;

10 output clk;

CONTENT

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平凡無奇的大學生,第三階段,0 comments,第二階段,今日第一階段考試結果9x9,模擬結果圖,模擬程式碼,define idle 2'b00,module cl clk ;,output clk;,reg clk;,initial,always,always @ posedge clk,endmodule,wire pb;,reg ready;,begin,endtask,module top;,reg pb;,wire ready;,integer s;,wire sysclk;,pb= 0;

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F9203843 | kingerzack.blogspot.com Reviews

https://kingerzack.blogspot.com

星期一, 5月 07, 2007. Posted by f9203843 @ 8:50 下午. 星期一, 4月 30, 2007. Posted by f9203843 @ 11:46 下午. 星期一, 4月 09, 2007. Define NUM STATE BITS 2. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Begin @(posedge sysclk) enter new state(`IDLE);. Posedge sysclk) enter new state(`COMPUTE123);. Reg clk,reset;.

INTERNAL PAGES

kingerzack.blogspot.com

1

F9203843: 第三階段考試

http://www.kingerzack.blogspot.com/2007/01/blog-post.html

星期四, 1月 04, 2007. Posted by f9203843 @ 9:21 下午. 21729;林鎮, 大葉大學, Taiwan. 31532;二階段考試測驗. Y第一階段通過這是結果. Y終於成功利用MaxPlus2圖示方式模擬出Hazard. 28204;試上課程式碼和實際使用SynaptiCAD. 31532;一階段自我練習實作使用程式碼. 31532;一階段自我練習實作結果成功 y. 21628;.新的部落格. 26356;慘了. 22909;神奇! 22238;家之後實做的全加器報告- 下.

2

F9203843: 十二月 2006

http://www.kingerzack.blogspot.com/2006_12_01_archive.html

星期二, 12月 26, 2006. Posted by f9203843 @ 8:43 下午. 21729;林鎮, 大葉大學, Taiwan. 31532;三階段. 31532;二階段. 20170;日第一階段考試結果9X9. 20170;日混合式除法機模擬圖和執行畫面. 31532;一階段乘法機完成. 3月12日紅綠燈挑戰. 26032;學期. 31532;四階段自我測驗Part-2. 31532;四階段自我測驗. 31532;三階段考試.

3

F9203843: 第二階段

http://www.kingerzack.blogspot.com/2007/04/blog-post_30.html

星期一, 4月 30, 2007. Posted by f9203843 @ 11:46 下午. 21729;林鎮, 大葉大學, Taiwan. 20170;日第一階段考試結果9X9. 20170;日混合式除法機模擬圖和執行畫面. 31532;一階段乘法機完成. 3月12日紅綠燈挑戰. 26032;學期. 31532;四階段自我測驗Part-2. 31532;四階段自我測驗. 31532;三階段考試. 31532;二階段考試測驗. Y第一階段通過這是結果.

4

F9203843: 今日第一階段考試結果9X9

http://www.kingerzack.blogspot.com/2007/04/9x9.html

星期一, 4月 09, 2007. Define NUM STATE BITS 2. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Begin @(posedge sysclk) enter new state(`IDLE);. Posedge sysclk) enter new state(`COMPUTE123);. Posedge sysclk) enter new state(`COMPUTE1234);. Task enter new state;. Input [`NUM STATE BITS-1:0] this state;.

5

F9203843: 三月 2007

http://www.kingerzack.blogspot.com/2007_03_01_archive.html

星期一, 3月 19, 2007. Posted by f9203843 @ 3:57 下午. 星期一, 3月 12, 2007. Reg clk,reset;. Wire [1:0]state,speed;. GYR G1(clk,reset,state,stop,speed,count);. 0 begin reset=1;clk=0; end. Repeat(30) #5 clk= clk;. Module GYR(clk,reset,state,stop,speed,count);. Parameter GREEN=2'b00,YELLOW=2'b01,RED=2'b10;. Input clk,reset;. Output [1:0]state,speed;. Reg [1:0]state,speed,states;. If(states= GREEN & count= 3'b000). Else if(states= YELLOW & count= 3'b000). Else if(states= RED & count= 3'b000). 星期一, 3月 05, 2007.

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bluerain11012.blogspot.com

計算機‧設計: 除法機 (混合模式)

http://bluerain11012.blogspot.com/2007/04/blog-post_6641.html

除法機程式碼，以SynaptiCAD模擬，模擬波形圖如下：. 訂閱：張貼留言 (Atom).

angellin198441.blogspot.com

林雅菁verilog作業: 2006.10

http://angellin198441.blogspot.com/2006_10_01_archive.html

星期二, 10月 24, 2006. 續)2006 10 17 2.5 Glitches andHazards(危障). 故ＦＡＣＢＣ' ＡＢ. Posted by 雅菁 at 2:07 下午. 2006 10 17( 2.5 Glitches and Hazards). 三個inputs之Karnaugh Map如下一般，我們只會圈ＡＣ及ＢＣ' 故ＦＡＣＢＣ'. 下圖為 F=AC BC' 佈線圖. 下圖為 F=AC BC' 的週期圖. Posted by 雅菁 at 1:22 下午. 星期二, 10月 03, 2006. B input:週期200.0 ns C output:週期207.5 ns. A input:週期100.0 ns. Posted by 雅菁 at 2:34 下午. 32396;)2006/12/26 第一階段測試- -part 3. 2006/12/26 第一階段測試- -part 3. 32396;)2006/12/05 第一階段測試- -part 2. 2006 10 17( 2.5 Glitches and Hazards).

lillian2714.blogspot.com

mp3xu4: 計算機設計

http://lillian2714.blogspot.com/2007/03/blog-post.html

今天上課初步認識課程中會用到的工具軟體SynaptiCAD,也將範例做了些試驗,因為之前都沒修過老師的課,對於軟體的使用並不了解,相信在使用幾次後就會熟練多了! 訂閱：張貼留言 (Atom).

lillian2714.blogspot.com

mp3xu4: 第一階段;乘法機之行為模式設計考試

http://lillian2714.blogspot.com/2007/05/blog-post.html

Define NUM STATE BITS 3. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Posedge sysclk) enter new state(`IDLE);. Ready = 1;. Posedge sysclk) enter new state(`INIT);. Posedge sysclk) enter new state(`INIT1);. Posedge sysclk) enter new state(`COMPUTE1);. Posedge sysclk) enter new state(`COMPUTE2);.

snoopy214.blogspot.com

95-上學期Verilog專用: ※ 第一階段的測試 ............(Continue)--Using Silos

http://snoopy214.blogspot.com/2006/11/continue-using-silos.html

Wednesday, November 15, 2006. 第一階段的測試 .(Continue)- Using Silos. Posted by snoopyyhc @ 3:24 AM. F9203822, 大葉大學電機系, Taiwan. View my complete profile. 8251;第一階段的測試 : Find Where 0-Hazard is? 2006/10/17 練習 - find Hazard. 2006/10/03 練習多工器 part2. 2006/09/28 Design Flow for HDL-based ASICs. 2006/09/26 practice the software of MAXPLUS2. 2006/09/21 校外教學- Verilog簡介. 20170;天真是糗到爆啦.

snoopy214.blogspot.com

95-上學期Verilog專用: December 2006

http://snoopy214.blogspot.com/2006_12_01_archive.html

Tuesday, December 19, 2006. 2006/12/19 第一階段終於 ending 啦朝第二階段邁進吧! 功能 : Test 電路圖是否有接錯. 終於做出來了.真是太高興了其實我是會做的.不曉得為什麼大家都做的很順利.而我卻非常的不順.上禮拜不是那邊怪怪的.就是這禮拜這裡怪怪的= = 而那些怪怪的原因就很像是卡到陰.實在很汗顏.我想我下一階段應該可以很快的做出來吧! 雖然代換成同一種邏輯閘(NAND or NOR)需要一些時間來算.不過這時候就是考驗到布林代數有沒有學好了.哈哈哈 A-ZA A-ZA Fighting! Posted by snoopyyhc @ 5:41 AM. Monday, December 11, 2006. 覺自己真的很笨.幹麻還去設周期阿.直接點旁邊的0 1值就好了= = 唉.不過下禮拜應該就可以把第一階段做出來了.拖太久了= =. Posted by snoopyyhc @ 11:40 PM. F9203822, 大葉大學電機系, Taiwan. View my complete profile.

snoopy214.blogspot.com

95-上學期Verilog專用: November 2006

http://snoopy214.blogspot.com/2006_11_01_archive.html

Tuesday, November 21, 2006. 的波形圖上看見 Hazard 只能嘗試的用Silos寫程式語言讓他在波型圖上出現Hazard 直到今天才知道方法的 :. 二在卡諾圖上找出Hazard在哪 , 再把其中已知的值. Posted by snoopyyhc @ 5:04 AM. 第一階段的測試 .End (使用maxplus2). F=[( A) ( C) ( D)]&[B ( C) ( D)]&[A ( C) D]&[A B ( C)]&[( A) B C]&[( A) C D]. Posted by snoopyyhc @ 4:36 AM. Wednesday, November 15, 2006. 第一階段的測試 .(Continue)- Using Silos. Posted by snoopyyhc @ 3:24 AM. 第一階段的測試 : Find Where 0-Hazard is? F= [( A) ( C) ( D)]&[A ( C) D]&[( A) C D]&[B ( C) ( D)]&[( A) B C ( D)];.

uoyroflla.blogspot.com

uoyroflla: 1226 第三階段測試

http://uoyroflla.blogspot.com/2006/12/1226.html

星期二, 12月 26, 2006. 訂閱：張貼留言 (Atom).

uoyroflla.blogspot.com

uoyroflla: 十一月 2006

http://uoyroflla.blogspot.com/2006_11_01_archive.html

星期二, 11月 21, 2006. 星期一, 11月 20, 2006. 下圖為(A,B,C,D)=(0110). 訂閱：文章 (Atom).

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F9203843

星期一, 5月 07, 2007. Posted by f9203843 @ 8:50 下午. 星期一, 4月 30, 2007. Posted by f9203843 @ 11:46 下午. 星期一, 4月 09, 2007. Define NUM STATE BITS 2. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Begin @(posedge sysclk) enter new state(`IDLE);. Posedge sysclk) enter new state(`COMPUTE123);. Reg clk,reset;.

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