angellin198441.blogspot.com
林雅菁verilog作業: 2006.10
http://angellin198441.blogspot.com/2006_10_01_archive.html
星期二, 10月 24, 2006. 續)2006 10 17 2.5 Glitches andHazards(危障). 故Ｆ ＡＣ ＢＣ' ＡＢ. Posted by 雅菁 at 2:07 下午. 2006 10 17( 2.5 Glitches and Hazards). 三個inputs之Karnaugh Map如下 一般，我們只會圈ＡＣ及ＢＣ' 故Ｆ ＡＣ ＢＣ'. 下圖為 F=AC BC' 佈線圖. 下圖為 F=AC BC' 的週期圖. Posted by 雅菁 at 1:22 下午. 星期二, 10月 03, 2006. B input:週期200.0 ns C output:週期207.5 ns. A input:週期100.0 ns. Posted by 雅菁 at 2:34 下午. 32396;)2006/12/26 第一階段測試- -part 3. 2006/12/26 第一階段測試- -part 3. 32396;)2006/12/05 第一階段測試- -part 2. 2006 10 17( 2.5 Glitches and Hazards).
kingerzack.blogspot.com
F9203843: 十月 2006
http://kingerzack.blogspot.com/2006_10_01_archive.html
星期二, 10月 24, 2006. Wire a,b;. System clock #100 clock1(a);. System clock #50 clock2(b);. Module system clock(clk);. Begin#(PERIOD/2) clk= clk;. PERIOD-PERIOD/2) clk= clk;. Endalways @ (posedge clk). Posted by f9203843 @ 2:44 下午. 星期二, 10月 17, 2006. Posted by f9203843 @ 10:02 下午. 星期二, 10月 03, 2006. Posted by f9203843 @ 8:43 下午. Posted by f9203843 @ 1:32 上午. 星期一, 10月 02, 2006. Posted by f9203843 @ 4:32 下午. 21729;林鎮, 大葉大學, Taiwan. 31532;三階段. 31532;二階段. 26032;學期. 31532;三階段考試.
fu007ghost.blogspot.com
怎麼會這樣: 十二月 2006
http://fu007ghost.blogspot.com/2006_12_01_archive.html
星期二, 12月 26, 2006. Wire a1,b1,c1,d1,f1,f2,f3,f4,f5,F;. Nand q1(a1,a,a);. Nand q2(b1,b,b);. Nand q3(c1,c,c);. Nand q4(d1,d,d);. Nand q5(f1,a1,c1);. Nand q6(f2,a1,b,d);. Nand q7(f3,a,c,d1);. Nand q8(f4,a,b1,c);. Nand q9(f5,f1,f2,f3,f4);. Nand q10(F,f5,f5,f5,f5);. A=0;b=0;c=0;d=0;. 200 a= a;. 100 b= b;. Wire a1,b1,c1,d1,f1,f2,f3,f4,f5,F;. Nand #3 q1(a1,a,a);. Nand #3 q2(b1,b,b);. Nand #3 q3(c1,c,c);. Nand #3 q4(d1,d,d);. Nand #3 q5(f1,a1,c1);. Nand #3 q6(f2,a1,b,c,d);/ 去除Hazard. Nand #3 q6(f2,a1,b,d);.
fu007ghost.blogspot.com
怎麼會這樣: 十一月 2006
http://fu007ghost.blogspot.com/2006_11_01_archive.html
星期二, 11月 21, 2006. Posted by 阿弟的天空 @ 9:53 下午. 星期三, 11月 15, 2006. 針對某4 inputs, 1 outpout 電路, 進行真值表, K-Map, 化簡. F=(B' C D')(A' C D')(A B C')(A C' D)(B C' D)(A B D)(A' B' C D'). F=(B' C D')(A' C D')(A B C')(A C' D)(B C' D)(A B D)(A' B' D'). Posted by 阿弟的天空 @ 12:42 上午. 38463;弟的天空. 31532;二階段練習. 32066;於發現Hazard. 31532;一階段. 21407;來是這樣. 20316;業一. 20170;天的課外活動! 20358;灌灌水ㄅ.把我淹沒.
f9203843.blogspot.com
憭批蔬敶剔��摰�
http://f9203843.blogspot.com/2006/09/blog-post.html
Notify Blogger about objectionable content. What does this mean? 撟喳 憭批飛 撠蝢憌敺頞= =. 鈭, 銋 29, 2006. Posted by f9203843 @ 12:12 銝. 銝, 銋 27, 2006. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Wire d,e,f;. Xor(d,a,b);. 頛舫摰,頛詨箇榛,頛詨亦榮,b. And(e,a,b);. 頛舫摰,頛詨箇榷,頛詨亦榮,b. Xor(Sum,d,Cin);. 頛舫摰,頛詨箇搴um,頛詨亦榛,Cin. And(f,d,Cin);. 頛舫摰,頛詨箇榻,頛詨亦榛,Cin. Or(Cout,f,e);. 頛舫摰,頛詨箇慢out,頛詨亦榻,e. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Assign {Cout,Sum}=a b Cin;. Input a,b,Cin;.
f9203843.blogspot.com
憭批蔬敶剔��摰�
http://f9203843.blogspot.com/2006/09/blog-post_115934459942445455.html
Notify Blogger about objectionable content. What does this mean? 撟喳 憭批飛 撠蝢憌敺頞= =. 鈭, 銋 29, 2006. Posted by f9203843 @ 12:12 銝. 銝, 銋 27, 2006. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Wire d,e,f;. Xor(d,a,b);. 頛舫摰,頛詨箇榛,頛詨亦榮,b. And(e,a,b);. 頛舫摰,頛詨箇榷,頛詨亦榮,b. Xor(Sum,d,Cin);. 頛舫摰,頛詨箇搴um,頛詨亦榛,Cin. And(f,d,Cin);. 頛舫摰,頛詨箇榻,頛詨亦榛,Cin. Or(Cout,f,e);. 頛舫摰,頛詨箇慢out,頛詨亦榻,e. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Assign {Cout,Sum}=a b Cin;. Input a,b,Cin;.
f9203843.blogspot.com
憭批蔬敶剔��摰�
http://f9203843.blogspot.com/2006/09/blog-post_26.html
Notify Blogger about objectionable content. What does this mean? 撟喳 憭批飛 撠蝢憌敺頞= =. 鈭, 銋 29, 2006. Posted by f9203843 @ 12:12 銝. 銝, 銋 27, 2006. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Wire d,e,f;. Xor(d,a,b);. 頛舫摰,頛詨箇榛,頛詨亦榮,b. And(e,a,b);. 頛舫摰,頛詨箇榷,頛詨亦榮,b. Xor(Sum,d,Cin);. 頛舫摰,頛詨箇搴um,頛詨亦榛,Cin. And(f,d,Cin);. 頛舫摰,頛詨箇榻,頛詨亦榛,Cin. Or(Cout,f,e);. 頛舫摰,頛詨箇慢out,頛詨亦榻,e. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Assign {Cout,Sum}=a b Cin;. Input a,b,Cin;.
f9203843.blogspot.com
憭批蔬敶剔��摰�
http://f9203843.blogspot.com/2006/09/blog-post_29.html
Notify Blogger about objectionable content. What does this mean? 撟喳 憭批飛 撠蝢憌敺頞= =. 鈭, 銋 29, 2006. Posted by f9203843 @ 12:12 銝. 銝, 銋 27, 2006. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Wire d,e,f;. Xor(d,a,b);. 頛舫摰,頛詨箇榛,頛詨亦榮,b. And(e,a,b);. 頛舫摰,頛詨箇榷,頛詨亦榮,b. Xor(Sum,d,Cin);. 頛舫摰,頛詨箇搴um,頛詨亦榛,Cin. And(f,d,Cin);. 頛舫摰,頛詨箇榻,頛詨亦榛,Cin. Or(Cout,f,e);. 頛舫摰,頛詨箇慢out,頛詨亦榻,e. Module fulladder 1(a,b,Cin,Sum,Cout);. Input a,b,Cin;. Output Sum,Cout;. Assign {Cout,Sum}=a b Cin;. Input a,b,Cin;.
kingerzack.blogspot.com
F9203843: 四月 2007
http://kingerzack.blogspot.com/2007_04_01_archive.html
星期一, 4月 30, 2007. Posted by f9203843 @ 11:46 下午. 星期一, 4月 09, 2007. Define NUM STATE BITS 2. Parameter TIME LIMIT = 110000; / 1250;. 50 clk = clk;. If ($time TIME LIMIT) #70 $stop;. Module slow div system(pb,ready,x,y,r3,sysclk);. Input pb,x,y,sysclk;. Output ready,r3;. Wire [11:0] x,y;. Reg [11:0] r1,r2,r3;. Reg [`NUM STATE BITS-1:0] present state;. Begin @(posedge sysclk) enter new state(`IDLE);. Posedge sysclk) enter new state(`COMPUTE123);. Posedge sysclk) enter new state(`COMPUTE1234);.
